L29S800F

LinkSmart Rev. No. Approved date A July 17 2002 L29S800F 8MEGABIT (1M×8 /512K×16) 3 VOLT CMOS FLASH MEMERY PRELIMINARY A Revision history History Initial issue Remark (purpose) Preliminary 1 071802 LinkSmart ! L29S800F 8MEGABIT (1M×8 /512K×16) 3 VOLT CMOS FLASH MEMERY PRELIMINARY A FEATURES Single 3.0 V read, program, and erase Minimizes system level power requirements Compatible with JEDEC-standard commands 2 Uses same software commands as E PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) Minimum 100,000 program/erase cycles High performance 70 ns maximum access time Sector erase architecture One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase Boot Code Sector Architecture T = Top sector B = Bottom sector TM Embedded Erase Algorithms Automatically pre-programs and erases the chip or any sector TM Embedded Program Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle completion Ready/Busy output (RY/ BY ) Hardware method for detection of program or erase cycle completion Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode Low VCC write inhibit ＜ 2.5 V Erase Suspend/Resume Suspend...