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B9940L Dataheets PDF



Part Number B9940L
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 1:18 Clock Distribution Buffer
Datasheet B9940L DatasheetB9940L Datasheet (PDF)

B9940L 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features • • • • • • 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 150-ps max. output-to-output skew Dual- or single-supply operation: — 3.3V core and 3.3V outputs — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin-compatible with MPC940L • Industrial temperature range: -40°C to 85°C • 32-pin LQFP package Description The B9940L is a lo.

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B9940L 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features • • • • • • 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 150-ps max. output-to-output skew Dual- or single-supply operation: — 3.3V core and 3.3V outputs — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin-compatible with MPC940L • Industrial temperature range: -40°C to 85°C • 32-pin LQFP package Description The B9940L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL- or an LVCMOS/LVTTL-compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V compatible and can drive two series-terminated 50Ω transmission lines. With this capability the B9940L has an effective fan-out of 1:36. Low output-to-output skews make the B9940L an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Block Diagram Pin Configuration VDDC 32 31 30 29 28 27 26 25 VSS Q0 Q1 Q2 Q3 Q4 Q5 VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL 0 1 VDDC 18 Q0-Q17 VSS VSS TCLK T C LK _S E L P E C L _C L K P E C L_ C LK # VDD VDDC 1 2 3 4 5 6 7 8 9 B9940L 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 Q6 Q7 Q8 VDD Q9 Q 10 Q 11 VSS Q17 Q16 Q15 Q14 Q13 VSS Q12 www.DataSheet4U.com Cypress Semiconductor Corporation Document #: 38-07105 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 26, 2002 VDDC B9940L Pin Description[1] Pin 5 6 3 Name PECL_CLK PECL_CLK# TCLK VDDC PWR I/O I, PU PECL Input Clock I, PD PECL Input Clock I, PD External Reference/Test Clock Input O Clock Outputs Description 9, 10, 11, 13, Q(17:0) 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 8, 16, 29 7, 21 TCLK_SEL VDDC VDD I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground 1, 2, 12, 17, 25 VSS Note: 1. PD = internal pull-down, PU = internal pull-up. www.DataSheet4U.com Document #: 38-07105 Rev. *C Page 2 of 5 B9940L Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................–65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD protection ............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter VIL VIH IIL IIH VPP VCMR VOL VOH IDDQ Zout Cin Description Input Low Voltage Input High Voltage Input Low Current[3] Input High Current[3] Peak-to-Peak Input Voltage PECL_CLK Common Mode PECL_CLK Range[4] VDD = 3.3V VDD = 2.5V IOL = 20 mA IOH = –20 mA, VDDC = 3.3V IOH = –20 mA, VDDC = 2.5V Quiescent Supply Current Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V Conditions All other inputs All other inputs Min. VSS 2.0 – – 500 VDD – 1.4 VDD – 1.0 – 2.4 1.8 – 9 11 – Typ. – – – – – – – – – – 2 14 18 4 [6] Max. 0.8 VDD –200 200 1000 VDD – 0.6 VDD – 0.6 0.5 – – 5 19 26 – Unit V V µA µA mV V V V V V mA Ω pF Output Low Voltage[5] Output High Voltage[5] AC Parameters VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C Parameter Fmax tPD tPD FoutDC Tskew Tskew(pp) Description Maximum Input Frequency PECL_CLK to Q Delay [7, 9] Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V Measured at VDD/2 VDD = 3.3V, Fin = 150 MHz VDD = 2.5V, Fin = 150 MHz PECL, VDDC = 3.3V Min. – 2.0 2.6 1.8 2.3 45 – – – Typ. – 3.5 4.0 3.3 3.8 – – – – Max. 200 4.0 5.2 3.8 4.4 55 150 200 1.4 Units MHz ns ns % ps ns TTL_CLK to Q Delay[7, 9] Output Duty Cycle[7, 8, 9] Output-to-Output Skew[7, 9] Part-to-Part Skew[10] – – 2.2 PECL, VDDC = 2.5V Notes: www.DataSheet4U.com 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power suppl sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is wit.


278LF-6-14 B9940L B9947


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