PX1012A

PX1011A/PX1012A PCI Express stand-alone X1 PHY Rev. 02 — 18 May 2006 Product data sheet 1. General description The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a, and Rev. 1.1. The PX1011A/1012A includes features such as clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices. The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. The 8-bit data interface operates at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O interfaces available in FPGA products. The PX1011A/1012A PCI Express PHY supports advanced power management functions. The PX1011AI/PX1012AI is for the industrial temperature range (−40 °C to +85 °C). 2. Features 2.1 PCI Express interface I I I I I I I I I I Compliant to PCI Express Base Specification 1.1 Single PCI Express 2.5 Gbit/s lane Data and clock recovery from serial stream Serializer and De-seri...