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HANBit
HDD16M72D9W
DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC
Part No. HDD16M72D9W
GENERAL DESCRIPTION
The HDD16M72D9W is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of nine CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD16M72D9W is a DIMM(Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
• Part Identification
HDD16M72D9W – 10A : HDD16M72D9W – 13A : HDD16M72D9W – 13B : 100MHz (CL=2) 133MHz (CL=2) 133MHz (CL=2.5)
• Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave)
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• Edge aligned data output, center aligned data input • Auto & Self refresh, 15.6us refresh interval (4K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1200 mil, double sided component
URL : www.hbe.co.kr REV 1.0 (November.2002)
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PIN ASSIGNMENT
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
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HDD16M72D9W
Front
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ * CK1 * /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19
PIN
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Back
A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY
PIN
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Frontl
VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD * /CS2 DQ48 DQ49 VSS * CK2 * /CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL
PIN
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ * BA2 DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
PIN
124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Front
VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY
PIN
154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back
/RAS DQ45 VDDQ /CS0 * /CS1 DM5 VSS DQ46 DQ47 * /CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
53 54 55 56 57 58 59 60 61
DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
145 146 147 148 149 150 151 152 153
VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
30 31
*These pins should be NC in the system which does not support SPD PIN A0~A11 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS7 DM0~DM7 CK0~CK2,/CK0~/CK2 CKE0 /CS0 /RAS /CAS
URL : www.hbe.co.kr REV 1.0 (November.2002)
PIN DESCRIPTION Address input Bank Select Address Data input/output Check bit(Data input/output) Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe Column Address strobe
2
PIN VDD VDDQ VREF VSPD VSS SA0~SA2 SDA SCL WP VDDIN NC
PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock Write protection VDD identification flag No connection
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FUNCTIONAL BLOCK DIAGRAM
HDD16M72D9W
w w w . D a t a S h e e t 4 U . n e t
URL : www.hbe.co.kr REV 1.0 (November.2002)
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD16M72D9W
Input Function CK and /CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except f.