WINBOND I/O. W83627SF Datasheet

W83627SF I/O. Datasheet pdf. Equivalent

Part W83627SF
Description WINBOND I/O
Feature W83627SF www.DataSheet4U.net W83627SF WINBOND I/O -1- Publication Release Date: May 31, 2005 Rev.
Manufacture Winbond
Datasheet
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W83627SF
W83627SF
www.DataSheet4U.net
W83627SF
WINBOND I/O
Publication Release Date: May 31, 2005
- 1 - Revision A1



W83627SF
W83627SF
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................ 6
2. FEATURES .................................................................................................................................... 7
3. PIN CONFIGURATION FOR W83627SF .................................................................................... 10
4. PIN DESCRIPTION...................................................................................................................... 11
4.1 LPC Interface ..................................................................................................................... 11
4.2 FDC Interface ..................................................................................................................... 12
4.3 Multi-Mode Parallel Port ..................................................................................................... 13
4.4 Serial Port Interface............................................................................................................ 18
4.5 KBC Interface ..................................................................................................................... 19
4.6 ACPI Interface .................................................................................................................... 19
4.7 Game Port & MIDI Port ...................................................................................................... 20
4.8 General Purpose I/O Port................................................................................................... 21
4.8.1 General Purpose I/O Port 1 (Power source is Vcc) ..............................................................21
4.8.2 General Purpose I/O Port 2 (Power source is Vcc) ..............................................................21
4.8.3 General Purpose I/O Port 3 (Power source is VSB) .............................................................21
4.9 SMART CARD Interface and General Purpose I/O port 7 (Powered by VCC except
SCPSNT# which is powered by VSB)................................................................................ 22
4.10 General Purpose I/O Port 4 (Powered by GP4PWR) ........................................................ 23
4.11 General Purpose I/O Port 5, 6 (Powered by VCC) ............................................................ 23
4.12 32KHz crystal oscillator...................................................................................................... 24
4.13 POWER PINS .................................................................................................................... 24
5. SMART CARD INTERFACE........................................................................................................ 25
5.1 Receiver Buffer Register (RBR, read only at "base address + 0" when BDLAB = 0)....... 25
5.2 Transmitter Buffer Register (TBR, write only at "base address + 0" when BDLAB = 0)... 25
5.3 Interrupt Control Register (ICR, at "base address + 1" when BDLAB = 0)....................... 25
5.4 Interrupt Status Register (ISR, read only at "base address + 2") ..................................... 26
5.5 Smart Card FIFO Control Register (SCFR, write only at "base address + 2") ................. 27
5.6 Smart Card Control Register (SCCR, write only at "base address + 3") .......................... 27
5.7 Interrupt Enable Register (IER, at "base address + 4") .................................................... 28
5.8 Smart Card Status Register (SCSR, at "base address + 5") ............................................ 28
5.9 Extended Control Register (ECR, at "base address + 7") ................................................ 29
5.10 Baud rate divisor Latch High and Baud rate divisor Latch Low (BHL and BLL at "base
address + 1" and "base address + 0" respectively when BDLAB = 1) ............................ 30
6. UART PORT ................................................................................................................................ 31
6.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B).................................. 31
6.2 Register Address................................................................................................................ 31
6.2.1 UART Control Register (UCR) (Read/Write) ........................................................................31
6.2.2 UART Status Register (USR) (Read/Write)..........................................................................34
-2-





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