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HMT125R7TFR8C Dataheets PDF



Part Number HMT125R7TFR8C
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 240pin DDR3 SDRAM Registered DIMM
Datasheet HMT125R7TFR8C DatasheetHMT125R7TFR8C Datasheet (PDF)

240pin DDR3 SDRAM Registered DIMM www.DataSheet4U.net DDR3 SDRAM Registered DIMM Based on 1Gb T-die HMT112R7TFR8C HMT125R7TFR8C HMT125R7TFR4C HMT151R7TFR8C HMT151R7TFR4C *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 0.1 / Dec. 2009 1 Revision History Revision No. 0.1 History Initial Release Draft Date Dec. 2009 Remark Preliminary Rev. 0.1 / Dec. 2009 2 Description Hynix Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronou.

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240pin DDR3 SDRAM Registered DIMM www.DataSheet4U.net DDR3 SDRAM Registered DIMM Based on 1Gb T-die HMT112R7TFR8C HMT125R7TFR8C HMT125R7TFR4C HMT151R7TFR8C HMT151R7TFR4C *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 0.1 / Dec. 2009 1 Revision History Revision No. 0.1 History Initial Release Draft Date Dec. 2009 Remark Preliminary Rev. 0.1 / Dec. 2009 2 Description Hynix Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations. Features • • • • • • • • • • • • • Power Supply: VDD=1.5V (1.425V to 1.575V) VDDQ = 1.5V (1.425V to 1.575V) Backward Compatible with 1.5V DDR3 Memory Module VDDSPD=3.0V to 3.6V Functionality and operations comply with the DDR3L SDRAM datasheet 8 internal banks Data transfer rates: PC3L-10600, PC3L-8500 Bi-Directional Differential Data Strobe 8 bit pre-fetch Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop) Supports ECC error correction and detection On-Die Termination (ODT) Temperature sensor with integrated SPD * This product is in compliance with the RoHS directive. Ordering Information Part Number HMT112R7TFR8C-G7/H9 HMT125R7TFR8C-G7/H9 HMT125R7TFR4C-G7/H9 HMT151R7TFR4C-G7/H9 HMT151R7TFR8C-G7 Density 1GB 2GB 2GB 4GB 4GB Organization 128Mx72 256Mx72 256Mx72 512Mx72 512Mx72 Component Composition 128Mx8(H5TQ1G83TFR)*9 128Mx8(H5TQ1G83TFR)*18 256Mx4(H5TQ1G43TFR)*18 256Mx4(H5TQ1G43TFR)*36 128Mx8(H5TQ1G83TFR)*36 # of ranks 1 2 2 2 4 FDHS X X X O O * In order to uninstall FDHS, please contact sales administrator Rev. 0.1 / Dec. 2009 3 Key Parameters MT/s DDR3-1066 DDR3-1333 Grade -G7 -H9 tCK (ns) 1.875 1.5 CAS Latency (tCK) 7 9 tRCD (ns) 13.125 13.5 tRP (ns) 13.125 13.5 tRAS (ns) 37.5 36 tRC (ns) 50.625 49.5 CL-tRCD-tRP 7-7-7 9-9-9 Speed Grade Frequency [MHz] Grade CL6 -G7 -H9 800 800 CL7 1066 1066 CL8 1066 1066 1333 1333 CL9 CL10 Remark Address Table 1GB(1Rx8) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(2Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2GB(1Rx4) 8K/64ms A0-A13 A0-A9, A11 BA0-BA2 1KB 4GB(2Rx4) 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 4GB(4Rx8) 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB Rev. 0.1 / Dec. 2009 4 Pin Descriptions Pin Name CK0 CK0 CK1 CK1 CKE[1:0] RAS Description Clock Input, positive line Clock Input, negative line Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Num ber 1 1 1 1 2 1 Pin Name ODT[1:0] DQ[63:0] CB[7:0] DQS[8:0] DQS[8:0] DM[8:0]/ DQS[17:9], TDQS[17:9] DQS[17:9], TDQS[17:9] EVENT TEST RESET VDD VSS VREFDQ VREFCA VTT VDDSPD Description On Die Termination Inputs Data Input/Output Data check bits Input/Output Data strobes Data strobes, negative line Data Masks / Data strobes, Termination data strobes Data strobes, negative line, Termination data strobes Reserved for optional hardware temperature sensing Memory bus test tool (Not Connected and Not Usable on DIMMs) Register and SDRAM control pin Power Supply Ground Reference Voltage for DQ Reference Voltage for CA Termination Voltage SPD Power Num ber 2 64 8 9 9 9 CAS WE S[3:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] SCL SDA SA[2:0] Par_In Err_Out Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Parity bit for the Address and Control bus Parity error found on the Address and Control bus 1 1 4 14 1 1 3 1 1 3 1 1 9 1 1 1 22 59 1 1 4 1 Rev. 0.1 / Dec. 2009 5 Input/Output Functional Descriptions Symbol CK0 CK0 CK1 CK1 Type IN IN IN IN Polarity Positive Line Negative Line Positive Line Negative Line Active High Function Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver. Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. Terminated but not used on RDIMMs. Terminated but not used on RDIMMs. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] f.


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