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CY2XP306
High-frequency Programmable PECL Clock Generation Module
Description
PRELIMINARY CY2XP306 High-frequency Programmable PECL Clock Generation Module Features 60 ps typical Cycle-to-Cycle Jitter 30 ps typical Output-Output Skew Phase-locked loop (PLL) multiplier select LVTTL or XO Input; Six LVPECL Outputs Selectable Output Divider (/2) 1–133 MHz Input Frequency Range 62.5–500 MHz Output Frequency Range 36-pin ...
Cypress Semiconductor
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