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Clock Oscillator. NBXHGA017 Datasheet

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Clock Oscillator. NBXHGA017 Datasheet






NBXHGA017 Oscillator. Datasheet pdf. Equivalent




NBXHGA017 Oscillator. Datasheet pdf. Equivalent





Part

NBXHGA017

Description

LVPECL Clock Oscillator

Manufacture

ON Semiconductor

Datasheet
Download NBXHGA017 Datasheet


ON Semiconductor NBXHGA017

NBXHGA017; NBXHGA017 2.5/3.3 V, 156.25 MHz LVPECL C lock Oscillator The NBXHGA017, single f requency, crystal oscillator (XO) is de signed to meet today’s requirements f or 2.5/3.3 V LVPECL clock generation ap plications. The device uses a high Q fu ndamental crystal and Phase Lock Loop ( PLL) multiplier to provide 156.25 MHz, ultra low jitter and phase noise LVPECL differential output.


ON Semiconductor NBXHGA017

. This device is a member of ON Semicond uctor’s PureEdget clock family that p rovides accurate and precision clock so lutions. Available in 5 mm x 7 mm SMD ( CLCC) package on 16 mm tape and reel in quantities of 100 and 1,000. Features http://onsemi.com MARKING DIAGRAM NBXHG A017 156.2500 AAWLYYWWG • • • • • • • • LVPECL Different ial Output Uses High Q Fundamental Mod.


ON Semiconductor NBXHGA017

e Crystal and PLL Multiplier Ultra Low J itter and Phase Noise − 0.5 ps (12 kH z − 20 MHz) Output Frequency − 156. 25 MHz Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range: 2.5 V ±5% or 3.3 V ±10% Total Freque ncy Stability − $50 PPM This is a Pb Free Device 6 PIN CLCC LN SUFFIX CAS E 848AB NBXHGA017= NBXHGA017 (±50 PPM ) 156.2500 = Output Frequency (.



Part

NBXHGA017

Description

LVPECL Clock Oscillator

Manufacture

ON Semiconductor

Datasheet
Download NBXHGA017 Datasheet




 NBXHGA017
NBXHGA017
2.5/3.3 V, 156.25 MHz
LVPECL Clock Oscillator
The NBXHGA017, single frequency, crystal oscillator (XO) is
designed to meet today’s requirements for 2.5/3.3 V LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide 156.25 MHz, ultra
low jitter and phase noise LVPECL differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 100 and 1,000.
Features
LVPECL Differential Output
Uses High Q Fundamental Mode Crystal and PLL Multiplier
Ultra Low Jitter and Phase Noise 0.5 ps (12 kHz 20 MHz)
Output Frequency 156.25 MHz
Hermetically Sealed Ceramic SMD Package
RoHS Compliant
Operating Range: 2.5 V ±5% or 3.3 V ±10%
Total Frequency Stability $50 PPM
This is a PbFree Device
Applications
Networking
Storage
Wireless Radio Communications
VDD
6
CLK CLK
54
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MARKING DIAGRAM
6 PIN CLCC
LN SUFFIX
CASE 848AB
NBXHGA017
156.2500
AAWLYYWWG
NBXHGA017= NBXHGA017 (±50 PPM)
156.2500 = Output Frequency (MHz)
AA = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
ORDERING INFORMATION
Device
Package Shipping
NBXHGA017LN1TAG CLCC6 1000 / Tape &
(PbFree)
Reel
NBXHGA017LNHTAG CLCC6 100 / Tape &
(PbFree)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
PLL
Clock
Multiplier
1 23
OE NC GND
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2010
www.DatAaSphreile, t240U1.0net Rev. 0
1
Publication Order Number:
NBXHGA017/D





 NBXHGA017
NBXHGA017
OE 1
NC 2
6 VDD
5 CLK
GND 3
4 CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ6
Symbol
OE
NC
GND
CLK
CLK
VDD
I/O
LVTTL/LVCMOS
Control Input
N/A
Power Supply
LVPECL Output
LVPECL Output
Power Supply
Description
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
No Connect.
Ground 0 V
NonInverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD 2 V.
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD 2 V.
Positive power supply voltage. Voltage should not exceed 2.5 V ±5% or 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRISTATE FUNCTION
OE Pin
Output Pins
Open
Active
HIGH Level
Active
LOW Level
High Z
Table 3. ATTRIBUTES
Characteristic
Value
Internal Default State Resistor
170 kW
ESD Protection
Human Body Model
Machine Model
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VDD Positive Power Supply
Iout LVPECL Output Current
GND = 0 V
Continuous
Surge
4.6 V
25 mA
50
TA Operating Temperature Range
40 to +85
°C
Tstg Storage Temperature Range
55 to +120
°C
Tsol Wave Solder
See Figure 5
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2





 NBXHGA017
NBXHGA017
Table 5. DC CHARACTERISTICS (VDD = 2.5 V ± 5%; 3.3 V ± 10%, GND = 0 V, TA = 40°C to +85°C) (Note 2)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
IDD Power Supply Current
95 105 mA
VIH OE Input HIGH Voltage
2000
VDD
mV
VIL OE Input LOW Voltage
GND 300
800 mV
IIH Input HIGH Current
OE
100
+100
mA
IIL Input LOW Current
OE
100
+100
mA
VOH Output HIGH Voltage
VDD1195
VDD945
mV
VOL Output LOW Voltage
VDD1945
VDD1600
mV
VOUTPP
Output Voltage Amplitude
700 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 W to VDD 2.0 V. See Figure 4.
Table 6. AC CHARACTERISTICS (VDD = 2.5 V ± 5%; 3.3 V ± 10%, GND = 0 V, TA = 40°C to +85°C) (Note 3)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
fCLKOUT
Output Clock Frequency
156.25
Df Frequency Stability NBXHGA017
(Note 4)
±50
FNOISE
PhaseNoise Performance
fCLKout = 156.25 MHz
(See Figure 3)
100 Hz of Carrier
1 kHz of Carrier
109
120
10 kHz of Carrier
127
Units
MHz
ppm
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz of Carrier
128
dBc/Hz
1 MHz of Carrier
135
dBc/Hz
10 MHz of Carrier
159
dBc/Hz
tjit(F)
tjitter
RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, PeaktoPeak
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
0.5 0.7 ps
1.5 8 ps
15 30 ps
Period, RMS
10,000 Cycles
1 4 ps
Period, PeaktoPeak
10,000 Cycles
10 20 ps
tOE/OD
tDUTY_CYCLE
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
200 ns
48 50 52 %
tR Output Rise Time (20% and 80%)
250 400 ps
tF Output Fall Time (80% and 20%)
250 400 ps
tstart Startup Time
Aging
1st Year
1 5 ms
3 ppm
Every Year After 1st
1 ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 W to VDD 2.0 V. See Figure 4.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
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3



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