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CY14MB064J Dataheets PDF



Part Number CY14MB064J
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 64-Kbit (8 K x 8) Serial (I2C) nvSRAM
Datasheet CY14MB064J DatasheetCY14MB064J Datasheet (PDF)

CY14MB064J CY14ME064J 64-Kbit (8 K × 8) Serial (I2C) nvSRAM 64-Kbit (8 K × 8) Serial (I2C) nvSRAM Features 64-Kbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 8 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL) ❐ Automatic STORE on power-down with a small.

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CY14MB064J CY14ME064J 64-Kbit (8 K × 8) Serial (I2C) nvSRAM 64-Kbit (8 K × 8) Serial (I2C) nvSRAM Features 64-Kbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 8 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL) ❐ Automatic STORE on power-down with a small capacitor (except for CY14MX064J1) ■ High reliability ❐ Infinite read, write, and RECALL cycles ❐ 1 million STORE cycles to QuantumTrap ❐ Data retention: 20 years at 85 C 2 ■ High speed I C interface ❐ Industry standard 100 kHz and 400 kHz speed ❐ Fast-mode Plus: 1 MHz speed ❐ High speed: 3.4 MHz ❐ Zero cycle delay reads and writes ■ Write protection ❐ Hardware protection using Write Protect (WP) pin ❐ Software block protection for 1/4, 1/2, or entire array 2 ■ I C access to special functions ❐ Nonvolatile STORE/RECALL ❐ 8 byte serial number ❐ Manufacturer ID and Product ID ❐ Sleep mode ■ ■ ■ Industry standard configurations ❐ Operating voltages: • CY14MB064J: VCC = 2.7 V to 3.6 V • CY14ME064J: VCC = 4.5 V to 5.5 V ❐ Industrial temperature ❐ 8- and 16-pin small outline integrated circuit (SOIC) package ❐ Restriction of hazardous substances (RoHS) compliant Overview The Cypress CY14MB064J/CY14ME064J combines a 64-Kbit nvSRAM[1] with a nonvolatile element in each memory cell. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14MX064J1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands. Configuration Feature AutoStore Software STORE Hardware STORE Slave Address pins CY14MX064J1 CY14MX064J2 CY14MX064J3 No Yes No A2, A1, A0 Yes Yes No A2, A1 Yes Yes Yes A2, A1, A0 Low power consumption ❐ Average active current of 1 mA at 3.4 MHz operation ❐ Average standby mode current of 150 µA ❐ Sleep mode current of 8 µA Logic Block Diagram Serial Number 8x8 VCC VCAP Manufacture ID/ Product ID Memory Control Register Command Register Sleep SDA SCL A2, A1, A0 WP 2 Power Control Block Quantrum Trap 8Kx8 SRAM 8Kx8 STORE RECALL Control Registers Slave Memory Slave Memory Address and Data Control I C Control Logic Slave Address Decoder Note 1. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet. www.DataSheet4U.net Cypress Semiconductor Corporation Document #: 001- 65051 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 6, 2011 [+] Feedback CY14MB064J CY14ME064J Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 I2C Interface ...................................................................... 4 Protocol Overview ............................................................ 4 I2C Protocol – Data Transfer ....................................... 4 Data Validity ...................................................................... 5 START Condition (S) ........................................................ 5 STOP Condition (P) .......................................................... 5 Repeated START (Sr) ....................................................... 5 Byte Format ....................................................................... 5 Acknowledge / No-acknowledge ..................................... 5 High Speed Mode (Hs-mode) ........................................... 6 Serial Data Format in Hs-mode ................................... 6 Slave Device Address ...................................................... 7 Memory Slave Device ................................................. 7 Control Registers Slave Device ................................... 7 Memory Control Register ............................................ 8 Command Register ..................................................... 8 Write Protection (WP) ....................................................... 9 AutoStore Operation ........................................................ 9 Hardware STORE and HSB pin Operation ..................... 9 Hardware RECALL (Power-Up) .................................. 9 Write Operation ............................................................... 10 Read Operation ............................................................... 10 Memory Slave Access .................................................... 10 Write nvSRA.


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