H5MS1262EFP

www.DataSheet4U.net 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2009 1 www.DataSheet4U.net 128Mbit MOBILE DDR SDRAM based on 2M x 4Bank x16 I/O Document Title 128Mbit (4Bank x 2M x 16bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 1.0 1.1 - Initial Draft - Define IDD specification -. Modify IDD Values(p.22 & p.23) , AC Characteristics(p24) -. Omit a typo in package information History Draft Date Sep. 2007 Feb. 2008 Jun. 2008 July. 2009 Remark Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2009 2 www.DataSheet4U.net Mobile DDR SDRAM 128Mbit (8M x 16bit) H5MS1262EFP Series FEATURES SUMMARY ● Mobile DDR SDRAM clock cycle ● MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per ● Mobile DDR SDRAM INTERFACE - x16 bus width: H5MS1262EFP - Multiplexed Address (Row address and Column address) ● CAS LATENCY - Programmable ...