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H27U8G8T2B Dataheets PDF



Part Number H27U8G8T2B
Manufacturers Hynix
Logo Hynix
Description 8 Gbit (1024 M x 8 bit) NAND Flash Memory
Datasheet H27U8G8T2B DatasheetH27U8G8T2B Datasheet (PDF)

www.DataSheet.co.kr 1 Preliminary H27U8G8T2B Series 8 Gbit (1024 M x 8 bit) NAND Flash 8 Gb NAND Flash H27U8G8T2B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.0 / Jul. 2008 1 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr 1 Preliminary H27U8G8T2B Series 8 Gbit (1024 M x 8 bit) NAND Flash Document Title 8 Gbit (1024 M x 8 b.

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www.DataSheet.co.kr 1 Preliminary H27U8G8T2B Series 8 Gbit (1024 M x 8 bit) NAND Flash 8 Gb NAND Flash H27U8G8T2B This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.0 / Jul. 2008 1 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr 1 Preliminary H27U8G8T2B Series 8 Gbit (1024 M x 8 bit) NAND Flash Document Title 8 Gbit (1024 M x 8 bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. History Draft Date Jul. 30. 2008 Remark Preliminary Rev 0.0 / Jul. 2008 2 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr 1 Preliminary H27U8G8T2B Series 8 Gbit (1024 M x 8 bit) NAND Flash FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications ELECTRONIC SIGNATURE - 1st cycle : Manufacturer Code - 2nd cycle : Device Code - 3rd cycle : Internal chip number, Cell Type, Number of Simultaneously Programmed Pages. - 4th cycle : Page size, Block size, Organization, Spare size - 5th cycle : Multiplane Information MULTIPLANE ARCHITECTURE - Array is split into two independent planes. Parallel operations on both planes are available, halving program, read and erase time. NAND INTERFACE - x8 bus width. - Address / Data Multiplexing - Pin-out compatibility for all densities COPY BACK PROGRAM - Fast Data Copy without external buffer CHIP ENABLE DON'T CARE - Simple interface with microcontroller SUPPLY VOLTAGE - 3.3 V device : Vcc = 2.7 V ~3.6 V STATUS REGISTER - Normal Status Register (Read/Program/Erase) MEMORY CELL ARRAY - (4 K + 128) bytes x 128 pages x 2048 blocks HARDWARE DATA PROTECTION - Device locked during Power transitions. PAGE SIZE - (4 K + 128 spare) Bytes DATA RETENTION - 5,000 Program/Erase cycles (with 4 bit / 528 byte ECC) - 10 years Data Retention BLOCK SIZE - (512 K + 16 K spare) Bytes PAGE READ / PROGRAM Random access : 60 us (max.) Sequential access : 25 ns (min.) Page program time : 800 us (typ.) Multi-Plane Program time (2 pages) : 800 us (typ.) PACKAGE - H27U8G8T2BTR-BX : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - H27U8G8T2BTR-BX (Lead & Halogen Free) FAST BLOCK ERASE - Block erase time: 2.5 ms (typ.) - Multi-Block Erase time (2 blocks) : 2.5 ms (typ.) Rev 0.0 / Jul. 2008 3 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr 1 Preliminary H27U8G8T2B Series 8 Gbit (1024 M x 8 bit) NAND Flash 1. SUMMARY DESCRIPTION Hynix NAND H27U8G8T2B Series have 1024 M x 8 bit with spare 32 M x 8 bit capacity. The device is offered in 3.3 V Vcc Power Supply, and with x8 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 2048 blocks, composed by 128 pages. Every cell holds two bits. A program operation allows to write the 4224 byte page in typical 800 us and an erase operation can be performed in typical 2.5 ms on a 512 K byte block. In addition to this, thanks to multi-plane architecture, it is possible to program 2 pages a time (one per each plane) or to read 2 pages a time (one per each plane) to erase 2 blocks a time (again, one per each plane). As a consequence, multiplane architecture allows program time reduction and erase time reduction. Data in the page can be read out at 25ns cycle time per byte. The I/O pins serve as the ports for address and data input/ output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. Data read out after copy back read (both for single and multiplane cases) is allowed. Even the write-intensive systems can take advantage of the H27U8G8T2B Series extended reliability of 5 K program/ erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE don't care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, sinc.


ATT7030A H27U8G8T2B 24C64A


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