D720200 UPD720200 Datasheet

D720200 Datasheet, PDF, Equivalent


Part Number

D720200

Description

UPD720200

Manufacture

NEC

Total Page 30 Pages
Datasheet
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D720200
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD720200
USB 3.0 HOST CONTROLLER
The PD720200 is the Universal Serial Bus 3.0 host controller, which complies with Universal Serial Bus 3.0
Specification, and Intels eXtensible Host Controller Interface (xHCI).
The PD720200 has PCI Express® bus interface, and it is applicable for PCI Express solution for host PC system.
The PD720200 works up to 5 Gbps for data transfer when connecting to USB 3.0 compliant peripherals, while
maintaining compatibility with existing USB peripheral devices.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
PD720200 User’s Manual : TBD
FEATURES
Compliant with Universal Serial Bus 3.0 specification
Revision 1.0, which is released by USB
Implementers Forum, Inc
- Supports the following speed data rate as
follows;
Low-speed (1.5 Mbps) / Full-speed (12 Mbps) /
High-speed (480 Mbps) / Super-speed (5 Gbps)
- Supports 2 downstream ports for all speeds
- Supports all USB compliant data transfer type as
follows; Control / Bulk / Interrupt / Isochronous
transfer
Compliant with Intels eXtensible Host Controller
Interface (xHCI) Specification revision 0.95
Support USB legacy function
Compliant with PCI Express® Base Specification 2.0
Supports ExpressCardTM Standard Release1.0
Supports PCI Express® Card Electromechanical
Specification Revision 2.0
Supports PCI Bus Power Management Interface
Specification revision 1.2
Operational registers are direct-mapped to PCI
memory space
Supports Serial Peripheral Interface (SPI) type ROM
System clock: 24 MHz crystal or 48MHz external
clock.
3.3 V and 1.05 V power supply
ORDERING INFORMATION
Part Number
PD720200F1-DAK-A
Package
176-pin plastic FBGA (10 10)
Remark
Lead-free product
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC
Electronics Corporation. The information in this document is subject to change without notice. Before using this document,
please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an
NEC Electronics sales representative for availability and additional information.
Document No. ISG-YD1-000127-05
Date Published April , 2009 CP (N)
2009
Datasheet pdf - http://www.DataSheet4U.net/

D720200
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BLOCK DIAGRAM
PD720200
PCI Express
Port
Super-speed
Controller
Interface
PCI Express
Gen2 Interface
(x 1)
xHCI
Controller
High-speed
Controller
Interface
Full/Low-speed
Controller
Interface
OSC/PLL
SPI
Interface
3.3V 1.05V
24MHz Xtal
External
48MHz clock input Serial ROM
USB3.0
SS Link
USB3.0
(Super-speed)
USB3.0
PHY
SS Root hub
Power SW
I/F
USB2.0
SIE
USB2.0
Root hub
USB2.0
(HS/FS/LS)
PHY
USB Port1
(SS)
USB Port2
(SS)
Port Power
Control
USB Port1
(HS/FS/LS)
USB Port2
(HS/FS/LS)
PCI Express
Gen2 Interface
xHCI Controller
Super-speed
Controller I/F
High-speed
Controller I/F
Full/Low-speed
Controller I/F
USB3.0 SS Link
USB3.0 SS
Root hub
USB3.0 PHY
USB2.0 SIE
USB2.0
Root hub
USB2.0 PHY
Power SW I/F
SPI Interface
PLL
OSC
: complies with PCI Express Gen2 interface, with 1 lane. This block includes link and
PHY layer.
: handles all supped required for USB 3.0, super-/high-/full-/low-speed. This block
includes register interface from system.
: handles super-speed operation in xHCI control block.
: handles high-speed operation in xHCI control block.
: handles full-/low-speed operation in xHCI control block.
: is link layer defined in USB 3.0 specification, which maintains Link connectivity with
USB devices.
: is a hub function in host controller for USB 3.0 port managing.
: for super-speed Tx/Rx
: is Serial Interface Engine, which controls USB 2.0 protocol sequence.
: is a hub function in host controller for USB 2.0 port managing.
: for high-/full-/low-speed Tx/Rx
: is connected to external power switch for port power control and over current detection.
: is connected to external serial ROM.
: Internal PLL.
: Internal oscillator block.
2 Preliminary Data Sheet
Datasheet pdf - http://www.DataSheet4U.net/


Features www.DataSheet.co.kr PRELIMINARY DATA SH EET MOS INTEGRATED CIRCUIT PD72020 0 USB 3.0 HOST CONTROLLER The PD72 0200 is the Universal Serial Bus 3.0 ho st controller, which complies with Univ ersal Serial Bus 3.0 Specification, and Intel’s eXtensible Host Controller I nterface (xHCI). The PD720200 has PC I Express® bus interface, and it is ap plicable for PCI Express solution for h ost PC system. The PD720200 works up to 5 Gbps for data transfer when conne cting to USB 3.0 compliant peripherals, while maintaining compatibility with e xisting USB peripheral devices. Detaile d function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. PD720200 User’s Manual : TBD FEAT URES  Compliant with Universal Seria l Bus 3.0 specification Revision 1.0, w hich is released by USB Implementers Fo rum, Inc - Supports the following speed data rate as follows; Low-speed (1.5 M bps) / Full-speed (12 Mbps) / High-speed (480 Mbps) / Super-speed (5 Gbps) - Suppo.
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