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EM68932DVKB Dataheets PDF



Part Number EM68932DVKB
Manufacturers Etron Technology
Logo Etron Technology
Description 4M x 32 Mobile DDR Synchronous DRAM
Datasheet EM68932DVKB DatasheetEM68932DVKB Datasheet (PDF)

www.DataSheet.co.kr EtronTech Etron Confidential Features Fast clock rate: 166/133 MHz Differential Clock CK & CK Bi-directional DQS Four internal banks, 1M x 32-bit for each bank Edge-aligned with read data, centered in write data Programmable Mode and Extended Mode Registers - CAS Latency: 2, or 3 - Burst length: 2, 4, or 8 - Burst Type: Sequential & Interleaved - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) • Individual byte write.

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www.DataSheet.co.kr EtronTech Etron Confidential Features Fast clock rate: 166/133 MHz Differential Clock CK & CK Bi-directional DQS Four internal banks, 1M x 32-bit for each bank Edge-aligned with read data, centered in write data Programmable Mode and Extended Mode Registers - CAS Latency: 2, or 3 - Burst length: 2, 4, or 8 - Burst Type: Sequential & Interleaved - PASR (Partial Array Self Refresh) - Auto TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) • Individual byte writes mask control • DM Write Latency = 0 • Precharge Standby Current = 100 µA • Self Refresh Current = 200 µA • Deep power-down Current = 10 µA max. at 85℃ • Auto Refresh and Self Refresh • 4096 refresh cycles / 64ms • No DLL (Delay Lock Loop), to reduce power; CK to DQS is not synchronized. • Power supplies: VDD & VDDQ = +1.8V+0.15V/-0.1V • Interface: LVCMOS • Ambient Temperature TA = -25 ~ 85℃, • 90-ball 8mm x 13mm VFBGA package - Pb and Halogen Free • • • • • • Part Number EM68932DVKB-6H EM68932DVKB-75H EM68932DVKB Advanced (Rev. 1.0 Aug. /2009) Table 1. Ordering Information Clock Frequency 166MHz 133MHz IDD6 Package 200 µA VFBGA 200 µA VFBGA 4M x 32 Mobile DDR Synchronous DRAM (SDRAM) VK: indicates VFBGA package B: indicates Generation Code H: indicates Pb and Halogen Free for VFBGA Package Figure 1. Ball Assignment (Top View) 1 A B C D E F G H J K L M N P R VSS VDDQ. VSSQ VDDQ VSSQ VDD CKE A9 A6 A4 VSSQ VDDQ VSSQ VDDQ VSS 2 DQ31 DQ29 DQ27 DQ25 DQS3 DM3 CK A11 A7 DM1 DQS1 DQ9 DQ11 DQ13 DQ15 3 VSSQ DQ30 DQ28 DQ26 DQ24 NC CK NC A8 A5 DQ8 DQ10 DQ12 DQ14 VSSQ … 7 VDDQ DQ17. DQ19 DQ21 DQ23 NC WE CS A10/AP A2 DQ7 DQ5 DQ3 DQ1 VDDQ 8 DQ16 DQ18 DQ20 DQ22 DQS2 DM2 CAS BA0 A0 DM0 DQS0 DQ6 DQ4 DQ2 DQ0 9 VDD VSSQ VDDQ VSSQ VDDQ VSS RAS BA1 A1 A3 VDDQ VSSQ VDDQ VSSQ VDD Overview The EM68932D is 134,217,728 bits of double data rate synchronous DRAM organized as 4 banks of 1,048,576 words by 32 bits. The synchronous operation with Data Strobe allows extremely high performance. EM68932D is applied to reduce leakage and refresh currents while achieving very high speed. I/O transactions are possible on both edges of the clock. The ranges of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Etron Technology, Inc. No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc. reserves the right to change products or specification without notice. Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr EtronTech Figure 2. lock Diagram PASR, DS CLOCK BUFFER EXTENDED MODE REGISTER EM68932DVKB CK CK CKE CS RAS CAS WE SELF REFRESH LOGIC & TIMER COMMAND DECODER CONTROL SIGNAL GENERATOR Row Decoder Row Decoder Row Decoder Row Decoder 1M x 32 CELL ARRAY (BANK #0) Column Decoder A10/AP COLUMN COUNTER MODE REGISTER 1M x 32 CELL ARRAY (BANK #1) Column Decoder A0 A9 A11 BA0 BA1 DQS0 ~ DQS3 DQ0 DQ31 ~ ~ ADDRESS BUFFER 1M x 32 CELL ARRAY (BANK #2) Column Decoder REFRESH COUNTER DATA STROBE BUFFER DQ Buffer 1M x 32 CELL ARRAY (BANK #3) Column Decoder DM0 DM3 ~ Etron Confidential 2 Rev. 1.0 Aug. 2009 Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr EtronTech Pin Descriptions Table 2. Pin Details of EM68932D Symbol CK, CK Type Input Description EM68932DVKB Differential Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK . Input and output data is referenced to the crossing of CK and CK (both directions of the crossing) Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self Refresh operation (all banks idle) or Active Power Down (Row Active in any bank). CKE is synchronous for all functions except for disabling outputs, which is asynchronous. Input buffers, excluding CK, CK and CKE, are disabled during Power Down and Self Refresh modes to reduce standby power consumption. Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. BA0 and BA1 also determine which mode register (MRS or EMRS) is loaded during a Mode Register Set command. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge). Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS is sampled HIGH. CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and WE signals and is latched at the positive edges of C.


K1818-MR EM68932DVKB GW39NC60VD


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