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Si3460
IEEE 802.3af PSE INTERFACE
Features
IEEE 802.3af™ compliant PSE and dc-dc controller Autonomous operation requires no host processor interface Complete reference design available, including Si3460 controller, PSE firmware, and schematic: Low-cost BOM with compact PCB footprint Operates directly from a +12 or +15 V isolated supply dc-dc controller generates –48 V PSE output for SELV compatibility with telephony interfaces Supports up to 15.4 W maximum output power (Class 0) Robust 3-point detection algorithm eliminates false detection events IEEE-compliant classification IEEE-compliant disconnect Inrush current control Short-circuit output fault protection LED status signal (detect, power good, output fault) UNH Interoperability Test Lab test report available Extended operating range (–40 to +85 °C) 11-Pin Quad Flat No-Lead (QFN) Tiny 3 x 3 mm PCB footprint; Pb-free, RoHS-compliant
AND
DC-DC CONTROLLER
Pin Assignments
Si3460
11 11
GATE CTRL1 VDD CTRL2 250KHZ
1 2 3 4 5 11 11
10 9
STATUS ISENSE RST VSENSE DETA
GND
8 7 6
11-pin QFN (3x3 mm) Top View—Pads on bottom of package
Applications
IEEE 802.3af endpoints and midspans Environment A and B PSEs Embedded PSEs Set-top boxes FTTH media converters Cable modem and DSL gateways
Description
The Si3460 is a single-port –48 V power management controller for IEEE 802.3af-compliant Power Sourcing Equipment (PSE). Designed to minimize system cost and ease of implementation in embedded PSE endpoint (switches) or midspan (power injector) applications, the Si3460 operates directly from a 12 or 15 V input supply and integrates a digital PWM-based dc-dc converter for generating the –48 V PSE output supply. The IEEE-required Powered Device (PD) detection feature uses a robust 3-point algorithm to avoid false detection events. The Si3460's reference design kit also provides full IEEE-compliant classification and PD disconnect. Intelligent protection circuitry includes input undervoltage lockout (UVLO), current limiting, and output short circuit protection. The Si3460 is designed to operate completely independently of host processor control. An LED status signal is provided to indicate the port status, including detect, power good, and output fault event information for use within the host system. The Si3460 is pin-programmable to support endpoint and midspan applications, as well as each of the different classification power levels specified by the IEEE 802.3af standard. A comprehensive reference design kit is available (Si3460-EVB), including a complete schematic and BOM (Bill-of-Materials) for the dcdc converter and PSE functions.
Preliminary Rev. 0.4 11/07 Copyright © 2007 by Silicon Laboratories Si3460
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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Si3460
1. Block Diagram
OTP Memory
Osc.
PWM DC/DC Controller: UVLO, Current Limiting, Short Circuit Protection
GATE 250KHZ VSENSE ISENSE
State Machine Control
RST STATUS
Config. & LED I/F
PSE Controller: Detection Classification Disconnect
CTRL1 CTRL2 DETA
Figure 1. Si3460 Block Diagram
2
Preliminary Rev. 0.4
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Si3460 TA B L E O F C O N T E N TS
Section Page
1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2. Si3460-EVB Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1. Si3460-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. Si3460 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4. Si3460-EVB Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1. PSE Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2. DC-DC Converter Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5. Si3460-EVB Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1. Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.2. Operating Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3. Operating Mode Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6.1. Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2. External Component Selection . ..