DatasheetsPDF.com

INTERNET DEVICE. ICS9UMS9633B Datasheet

DatasheetsPDF.com

INTERNET DEVICE. ICS9UMS9633B Datasheet






ICS9UMS9633B DEVICE. Datasheet pdf. Equivalent




ICS9UMS9633B DEVICE. Datasheet pdf. Equivalent





Part

ICS9UMS9633B

Description

ULTRA MOBILE PC/MOBILE INTERNET DEVICE



Feature


www.DataSheet.co.kr Advance Information ULTRA MOBILE PC/MOBILE INTERNET DEVICE Recommended Application: Poulsbo Based Ultra-Mobile PC (UMPC) ICS9UMS9633B Features/Benefits: • • • • • • • Supports Dothan ULV CPUs with 6 7 to 167 MHz CPU outputs Dedicated TEST /SEL and TEST/MODE pins saves isolation resistors on pins CPU STOP# input for power manangment Fully integrate.
Manufacture

IDT

Datasheet
Download ICS9UMS9633B Datasheet


IDT ICS9UMS9633B

ICS9UMS9633B; d Vreg Integrated series resistors on di fferential outputs 1.5V VDD IO operatio n, 3.3V VDD core and REF supply pin for REF Industrial Temperature (-40 to +85 C) version available Output Features: • • • • • 3 - CPU low power d ifferential push-pull pairss 3 - SRC lo w power differential push-pull pairs 1 - LCD100 SSCD low power differential pu sh-pull pair 1 - DOT96 low p.


IDT ICS9UMS9633B

ower differential push-pull pair 1 - REF , 14.31818MHz, 3.3V SE output SSOP Pin Configuration REF GNDREF VDDCORE_3.3 F SC_L TEST_MODE TEST_SEL SCLK SDATA VDDC ORE_3.3 VDDIO_1.5 DOT96C_LPR DOT96T_LPR GNDDOT GNDLCD LCD100C_LPR LCD100T_LPR VDDIO_1.5 VDDCORE_3.3 *CR#0 GNDSRC SRCC 0_LPR SRCT0_LPR *CR#1 VDDCORE_3.3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24.


IDT ICS9UMS9633B

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF _3.3 X1 X2 CLKPWRGD#/PD_3.3 CPU_STOP# C PUT0_LPR CPUC0_LPR VDDIO_1.5 GNDCPU CPU T1_LPR CPUC1_LPR VDDCORE_3.3 VDDIO_1.5 GNDCPU CPUT2_LPR CPUC2_LPR FSB_L *CR#2 SRCT2_LPR SRCC2_LPR GNDSRC SRCT1_LPR SR CC1_LPR VDDIO_1.5 48 SSOP Package * in dicates inputs with internal pull up of ~10Kohm to 3.3V I.

Part

ICS9UMS9633B

Description

ULTRA MOBILE PC/MOBILE INTERNET DEVICE



Feature


www.DataSheet.co.kr Advance Information ULTRA MOBILE PC/MOBILE INTERNET DEVICE Recommended Application: Poulsbo Based Ultra-Mobile PC (UMPC) ICS9UMS9633B Features/Benefits: • • • • • • • Supports Dothan ULV CPUs with 6 7 to 167 MHz CPU outputs Dedicated TEST /SEL and TEST/MODE pins saves isolation resistors on pins CPU STOP# input for power manangment Fully integrate.
Manufacture

IDT

Datasheet
Download ICS9UMS9633B Datasheet




 ICS9UMS9633B
www.DataSheet.co.kr
Advance Information
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
ICS9UMS9633B
Recommended Application:
Poulsbo Based Ultra-Mobile PC (UMPC)
Output Features:
• 3 - CPU low power differential push-pull pairss
• 3 - SRC low power differential push-pull pairs
• 1 - LCD100 SSCD low power differential
push-pull pair
• 1 - DOT96 low power differential push-pull
pair
• 1 - REF, 14.31818MHz, 3.3V SE output
SSOP Pin Configuration
Features/Benefits:
• Supports Dothan ULV CPUs with 67 to 167
MHz CPU outputs
• Dedicated TEST/SEL and TEST/MODE pins
saves isolation resistors on pins
• CPU STOP# input for power manangment
• Fully integrated Vreg
• Integrated series resistors on differential
outputs
• 1.5V VDD IO operation, 3.3V VDD core and
REF supply pin for REF
• Industrial Temperature (-40 to +85C) version
available
REF 1
GNDREF 2
VDDCORE_3.3 3
FSC_L 4
TEST_MODE 5
TEST_SEL 6
SCLK 7
SDATA 8
VDDCORE_3.3 9
VDDIO_1.5 10
DOT96C_LPR 11
DOT96T_LPR 12
GNDDOT 13
GNDLCD 14
LCD100C_LPR 15
LCD100T_LPR 16
VDDIO_1.5 17
VDDCORE_3.3 18
*CR#0 19
GNDSRC 20
SRCC0_LPR 21
SRCT0_LPR 22
*CR#1 23
VDDCORE_3.3 24
48 VDDREF_3.3
47 X1
46 X2
45 CLKPWRGD#/PD_3.3
44 CPU_STOP#
43 CPUT0_LPR
42 CPUC0_LPR
41 VDDIO_1.5
40 GNDCPU
39 CPUT1_LPR
38 CPUC1_LPR
37 VDDCORE_3.3
36 VDDIO_1.5
35 GNDCPU
34 CPUT2_LPR
33 CPUC2_LPR
32 FSB_L
31 *CR#2
30 SRCT2_LPR
29 SRCC2_LPR
28 GNDSRC
27 SRCT1_LPR
26 SRCC1_LPR
25 VDDIO_1.5
48 SSOP Package
* indicates inputs with internal pull up of ~10Kohm to 3.3V
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1
1423—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/




 ICS9UMS9633B
www.DataSheet.co.kr
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
SSOP Pin Description
PIN #
PIN NAME
1 REF
2 GNDREF
3 VDDCORE_3.3
4 FSC_L
5 TEST_MODE
6 TEST_SEL
7 SCLK
8 SDATA
9 VDDCORE_3.3
10 VDDIO_1.5
11 DOT96C_LPR
12 DOT96T_LPR
13 GNDDOT
14 GNDLCD
15 LCD100C_LPR
16 LCD100T_LPR
17 VDDIO_1.5
18 VDDCORE_3.3
19 *CR#0
20 GNDSRC
21 SRCC0_LPR
22 SRCT0_LPR
23 *CR#1
24 VDDCORE_3.3
TYPE
DESCRIPTION
OUT 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
IN 1 = All outputs are tri-stated for test
0 = All outputs behave normally.
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
OUT True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
OUT Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
OUT
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
IN Clock request for SRC0, 0 = enable, 1 = disable
PWR Ground pin for the SRC outputs
OUT
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
IN Clock request for SRC1, 0 = enable, 1 = disable
PWR 3.3V power for the PLL core
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
2
1423—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/




 ICS9UMS9633B
www.DataSheet.co.kr
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
Advance Information
SSOP Pin Description (continued)
PIN #
PIN NAME
25 VDDIO_1.5
26 SRCC1_LPR
27 SRCT1_LPR
28 GNDSRC
29 SRCC2_LPR
30 SRCT2_LPR
31 *CR#2
32 FSB_L
33 CPUC2_LPR
34 CPUT2_LPR
35 GNDCPU
36 VDDIO_1.5
37 VDDCORE_3.3
38 CPUC1_LPR
39 CPUT1_LPR
40 GNDCPU
41 VDDIO_1.5
42 CPUC0_LPR
43 CPUT0_LPR
44 CPU_STOP#
TYPE
DESCRIPTION
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
PWR Ground pin for the SRC outputs
OUT Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
OUT True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
IN Clock request for SRC2, 0 = enable, 1 = disable
IN
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
PWR Ground pin for the CPU outputs
PWR Power supply for low power differential outputs, nominal 1.5V.
OUT Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor. No 50 ohm resistor to GND needed.
OUT True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor. No 50 ohm resistor to GND needed.
IN Stops all CPU clocks, except those set to be free running clocks
45 CLKPWRGD#/PD_3.3
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
IN are valid and are ready to be sampled. This is an active low input. / Asynchronous
active high input pin used to place the device into a power down state.
46 X2
47 X1
48 VDDREF_3.3
OUT Crystal output, Nominally 14.318MHz
IN Crystal input, Nominally 14.318MHz.
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
3
1423—01/20/09
Datasheet pdf - http://www.DataSheet4U.net/






Recommended third-party ICS9UMS9633B Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)