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Flash Memory. MX30LF1G08AA Datasheet

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Flash Memory. MX30LF1G08AA Datasheet






MX30LF1G08AA Memory. Datasheet pdf. Equivalent




MX30LF1G08AA Memory. Datasheet pdf. Equivalent





Part

MX30LF1G08AA

Description

1G-bit NAND Flash Memory

Manufacture

Macronix International

Datasheet
Download MX30LF1G08AA Datasheet


Macronix International MX30LF1G08AA

MX30LF1G08AA; MX30LF1G08AA 1G-bit NAND Flash Memory MX30LF1G08AA P/N: PM1113 1 REV. 0.06, FEB. 08, 2012 MX30LF1G08AA Contents 1. FEATURES........................... ....................................... ....................................... ...............................4 2. GE NERAL DESCRIPTIONS..................... ....................................... ...................


Macronix International MX30LF1G08AA

................................4 Figure 1. MX30LF1G08AA Logic Diagram. ....... ....................................... ....................................... ........ 4 2-1. 3-1. ORDERING INFOR MATION................................. ....................................... ............................5 PIN DESCR IPTIONS................................ ...................


Macronix International MX30LF1G08AA

........................................ .....................7 3. PIN CONFIGU RATIONS................................ ....................................... ....................................... ......6 4. PIN FUNCTIONS. ............ ....................................... ....................................... .....................................8 5. BLOCK DIAGRAM..



Part

MX30LF1G08AA

Description

1G-bit NAND Flash Memory

Manufacture

Macronix International

Datasheet
Download MX30LF1G08AA Datasheet




 MX30LF1G08AA
MX30LF1G08AA
MX30LF1G08AA
1G-bit NAND Flash Memory
P/N: PM1113
REV. 1.5, SEP. 17, 2014
1





 MX30LF1G08AA
MX30LF1G08AA
Contents
1. FEATURES........................................................................................................................................4
2. GENERAL DESCRIPTIONS..............................................................................................................4
Figure 1. Logic Diagram.......................................................................................................................... 4
2-1. ORDERING INFORMATION....................................................................................................5
3. PIN CONFIGURATIONS....................................................................................................................6
3-1. PIN DESCRIPTIONS...............................................................................................................7
4. PIN FUNCTIONS................................................................................................................................8
5. BLOCK DIAGRAM.............................................................................................................................9
Figure 2. AC Waveform for Command / Address / Data Latch Timing.................................................. 10
Figure 3. AC Waveforms for Address Input Cycle................................................................................. 10
6. DEVICE OPERATIONS....................................................................................................................10
Figure 4. AC Waveforms for Command Input Cycle............................................................................. 11
Figure 5. AC Waveforms for Data Input Cycle...................................................................................... 11
Figure 6. AC Waveforms for Read Cycle.............................................................................................. 12
Figure 7. AC Waveforms for Read Operation (Intercepted by CE#)..................................................... 13
Figure 8. Read Operation with CE# Don't Care.................................................................................... 14
Figure 9. AC Waveforms for Sequential Data Out Cycle (After Read).................................................. 14
Figure 10. AC Waveforms for Random Data Output............................................................................. 15
Figure 11. AC Waveforms for Cache Read........................................................................................... 17
Figure 12. AC Waveforms for Program Operation after Command 80H............................................... 18
Figure 13. AC Waveforms for Random Data In (For Page Program).................................................... 19
Figure 14. Program Operation with CE# Don't Care............................................................................. 20
Figure 15-1. AC Waveforms for Cache Program ................................................................................. 22
Figure 15-2. Sequence of Cache Program .......................................................................................... 23
Figure 16. AC Waveforms for Erase Operation..................................................................................... 24
Figure 17. AC Waveforms for ID Read Operation................................................................................. 25
Figure 18. AC Waveforms for Status Read Operation.......................................................................... 26
Figure 19. Reset Operation................................................................................................................... 27
7. PARAMETERS.................................................................................................................................28
7-1. ABSOLUTE MAXIMUM RATINGS........................................................................................28
Figure 20. Device Under Test................................................................................................................ 30
Table 1. Operating Range..................................................................................................................... 29
Table 2. DC Characteristics................................................................................................................... 29
Table 3. Capacitance............................................................................................................................. 29
P/N: PM1113
REV. 1.5, SEP. 17, 2014
2





 MX30LF1G08AA
MX30LF1G08AA
Table 4. AC Testing Conditions............................................................................................................. 30
Table 5. Program, Read and Erase Characteristics.............................................................................. 30
Table 6. AC Characteristics over Operating Range............................................................................... 31
8. SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT.......................................................32
Table 7. Address Allocation................................................................................................................... 32
9. OPERATION MODES: LOGIC AND COMMAND TABLES.............................................................33
Figure 21. Bit Assignment (HEX Data).................................................................................................. 34
Table 8. Logic Table.............................................................................................................................. 33
Table 9. HEX Command Table.............................................................................................................. 34
Table 10. Status Output......................................................................................................................... 35
Table 11. ID Codes Read Out by ID Read Command 90H................................................................... 35
Table 12. The Definition of 3rd Code of ID Table................................................................................. 36
Table 13. The Definition of 4th Code of ID Table.................................................................................. 36
9-1. R/B#: TERMINATION FOR THE READY/BUSY# PIN (R/B#)..............................................37
Figure 22. R/B# Pin Timing Information................................................................................................ 37
9-2. POWER ON/OFF SEQUENCE..............................................................................................38
Figure 23. Power On/Off Sequence...................................................................................................... 38
Figure 24. Enable Programming........................................................................................................... 39
Figure 25. Disable Programming.......................................................................................................... 39
Figure 26. Enable Erasing..................................................................................................................... 39
Figure 27. Disable Erasing.................................................................................................................... 39
10. SOFTWARE ALGORITHM...............................................................................................................40
10-1. INVALID BLOCKS (BAD BLOCKS)......................................................................................40
Figure 28. Bad Blocks........................................................................................................................... 40
Table 14. Valid Blocks........................................................................................................................... 40
10-2. BAD BLOCK TEST FLOW....................................................................................................41
10-3. FAILURE PHENOMENA FOR READ/PROGRAM/ERASE OPERATIONS..........................41
Table 15. Failure Modes........................................................................................................................ 41
10-4. PROGRAM.............................................................................................................................42
Figure 30. Failure Modes...................................................................................................................... 42
Figure 31. Program Flow Chart............................................................................................................. 42
10-5. ERASE...................................................................................................................................42
Figure 32. Erase Flow Chart................................................................................................................. 43
Figure 33. Read Flow Chart.................................................................................................................. 43
11. PACKAGE INFORMATION..............................................................................................................45
12. REVISION HISTORY .......................................................................................................................47
P/N: PM1113
REV. 1.5, SEP. 17, 2014
3



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