TC74HC112AP

TC74HC112AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC112AP, TC74HC112AF Dual J-K Flip Flop with Preset and Clear The TC74HC112A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse. CLR and PR are independent of the clock and are actived by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: fmax = 67 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 2 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 4 mA (min) Balanced propagation delays: tpLH ∼− tpHL Wide operating voltage range: VCC (opr) = 2 to 6 V Pin and function compatible with 74LS112 Pin Assignment TC74HC112AP TC74HC112AF Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Start of commercial production 1988-05 1 2014-03-01 IEC Logic Symbol TC74HC112AP/AF Truth Table Inputs CLR PR J K L H X X H L X X L L X X H H L L H H L H H H H L H H H H H H X X X: Don’t care Outputs CK Q Q Function X L ...