Document
Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter
IDT82P5088
FEATURES
• • • • • • Eight channel T1/E1/J1 long haul/short haul line interfaces Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024 KHz Programmable T1/E1/J1 switchability allowing one bill of material for any line condition 3.3 V and 1.8 V power supply with 5 V tolerant inputs Meets or exceeds specifications in - ANSI T1.102, T1.403 and T1.408 - ITU I.431, G.703,G.736, G.775 and G.823 - ETSI 300-166, 300-233 and TBR 12/13 - AT&T Pub 62411 Per channel software selectable on: - Wave-shaping templates for short haul and long haul LBO (Line Build Out) - Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω) - Adjustment of arbitrary pulse shape - JA (Jitter Attenuator) position (receive path and transmit path) - Single rail/dual rail system interfaces - B8ZS/HDB3/AMI line encoding/decoding - Active edge of transmit clock (TCLK) and receive clock (RCLK) Active level of transmit data (TDATA) and receive data (RDATA) Receiver or transmitter power down High impedance setting for line drivers PRBS (Pseudo Random Bit Sequence) generation and detection with 215-1 PRBS polynomials for E1 - QRSS (Quasi Random Sequence Signals) generation and detection with 220-1 QRSS polynomials for T1/J1 - 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS error counter - Analog loopback, Digital loopback, Remote loopback and Inband loopback Per channel cable attenuation indication Adaptive receive sensitivity Non-intrusive monitoring per ITU G.772 specification Short circuit protection for line drivers LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection JTAG interface Supports serial control interface, Motorola and Intel Non-Multiplexed interfaces Package: Available in 256-pin PBGA Green package options available -
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DESCRIPTION
The IDT82P5088 is an eight port line intereface that can be configured per port to any combination of T1, E1 or J1 ports. In receive path, an Adaptive Equalizer is integrated to remove the distortion introduced by the cable attenuation. The IDT82P5088 also performs clock/data recovery, AMI/ B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In transmit path, there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper, LBOs and Jitter Attenuator for each channel. The Jitter Attenuators in transmit path and receive path both can be disabled. The IDT82P5088 supports both Single Rail and Dual Rail system interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in each channel, and different types of loopbacks can be set on a per channel basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110 Ω and 120 Ω are selectable on a per channel basis. The chip also provides driver short-circuit protection and supports JTAG boundary scanning. The IDT82P5088 can be used in SDH/SONET, LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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2009 Integrated Device Technology, Inc.
February 5, 2009
DSC-7216/Datasheet pdf - http://www.DataSheet4U.net/
IDT82P5088
FUNCTIONAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
One of the Eight Identical Channels
LOS/AIS Detector RTIPn RRINGn B8ZS/ HDB3/AMI Decoder Jitter Attenuator Data Slicer Adaptive Equalizer Clock and Data Recovery Receiver Internal Termination
LOSn
RCLKn RDn/RDPn CVn/RDNn
PRBS Detector IBLC Detector
Remote Loopback
Jitter Attenuator Line Driver
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Digital Loopback
Waveform Shaper/LBO
Analog Loopback
TTIPn Transmitter Internal Termination TRINGn
Figure-1 Block Diagram
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
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Control Interface
TCLKn TDn/TDPn TDNn
B8ZS/ HDB3/AMI Encoder
PRBS Generator IBLC Generator TAOS
Clock Generator
JTAG TAP
VDDDIO / VDDDC / VDDAR / VDDAT / VDDAX / VDDAP / VDDAB
G.772 Monitor
TDO TDI TMS TCK TRST
GPIO[1:0] RESET THZ A[10:0] D[7:1] D[0]/SDO CS REFR RW/WR/SDI DS/RD/SCLK MPM SPIEN INT
REFB_OUT REFA_OUT CLK_SEL[2:0] OSCO OSCI CLK_GEN_1.544 CLK_GEN_2.048
GNDD / GNDA
February 5, 2009
Datasheet pdf - http://www.DataSheet4U.net/
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Tables of Contents
1 2 3 IDT82P5088 PIN CONFIGURATIONS .......................................................................................... 9 PIN DESCRIPTION ..................................................................................................................... 10 FUNCTIONAL DESCRIPTION .................................................................................................... 17 3.1 T1/E1/J1 MODE SELECTION .......................................................................................... 17 3.2 TRANSMIT PATH ...........