GS8170DD36C-300

GS8170DD36C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp Features Double Data Rate Read and Write mode Late Write; Pipelined read operation JEDEC-standard SigmaRAM™ pinout and package 1.8 V +150/–100 mV core power supply 1.8 V CMOS Interface ZQ controlled user-selectable output drive strength Dual Cycle Deselect Burst Read and Write option Fully coherent read and write pipelines Echo Clock outputs track data output drivers 2 user-programmable chip enable inputs IEEE 1149.1 JTAG-compliant Serial Boundary Scan 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package Pin-compatible with future 36Mb, 72Mb, and 144Mb devices 18Mb Σ1x2Lp CMOS I/O Double Data Rate SigmaRAM™ 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O cueing and data transfer rates. The ΣRAM™ family standard allows a user to implement the interface protocol best suited to the task at hand. Functional Description Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. In DDR mode the device captures Data In on both rising and falling edges of clock and drives data on both clock edges as well. Because the DDR ΣRAM always transfers data in two halves, A0 is internally set to 0 f...