GS8170DD18C-250

Preliminary GS8170DD18/36C-333/300/250 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x2Lp Double Data Rate SigmaRAM™ SRAM 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features Double Data Rate Read and Write mode JEDEC-standard SigmaRAM™ pinout and package 1.8 V +150/–100 mV core power supply 1.5 V or 1.8 V I/O supply Pipelined read operation Fully coherent read and write pipelines Echo Clock outputs track data output drivers ZQ mode pin for user-selectable output drive strength 2 user-programmable chip enable inputs for easy depth expansion IEEE 1149.1 JTAG-compatible Boundary Scan 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package Pin-compatible with future 36Mb, 72Mb, and 144Mb devices - 333 3.0 ns 1.6 ns Pipeline mode tKHKH tKHQV Bottom View 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array DDR mode the device captures Data In on both rising and falling edges of clock and drives data on both clock edges as well. Because the DDR ΣRAM always transfers data in two halves, A0 is internally set to 0 for the first half of each read or write transfer, and automatically incremented to 1 for the falling edge transfer. The address field of a DDR ΣRAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512k addressable index). In Pipeline mode, Single Data Rate (SDR) ΣRAMs incorporate a rising-edge-triggered output register. In DDR mode, risingand falling-edge-triggered output registers are empl...