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GS8170DW72C-250 Dataheets PDF



Part Number GS8170DW72C-250
Manufacturers GSI Technology
Logo GSI Technology
Description (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM
Datasheet GS8170DW72C-250 DatasheetGS8170DW72C-250 Datasheet (PDF)

Preliminary GS8170DW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™ 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O Features • Double Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock .

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Preliminary GS8170DW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™ 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O Features • Double Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes) • 2 user-programmable chip enable inputs • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices Key Fast Bin Specs Cycle Time Access Time Symbol tKHKH tKHQV - 333 3.0 ns 1.6 ns www.DataSheet.co.kr Bottom View 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array Functional Description Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. ΣRAMs support pipelined reads utilizing a rising-edgetriggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. SigmaRAM Family Overview GS8170DW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems. ΣRAMs are offered in a number of configurations including Late Write, Double Late Write, and Double Data Rate (DDR). The logical differences between the protocols employed by these RAMs mainly involve various approaches to write cueing and data transfer rates. The ΣRAM™ family standard allows a user to implement the interface protocol best suited to the task at hand. ΣRAMs are implemented with high performance CMOS technology and are packaged in a 209-bump BGA. Rev: 2.01 5/2003 1/30 © 2002, GSI Technology, Inc. Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative. Datasheet pdf - http://www.DataSheet4U.net/ Preliminary GS8170DW36/72C-333/300/250/200 SigmaRAM Pinouts 256k x 72 Common I/O—Top View 1 A B C D E F G H J K L M N P R T U V W • 2002.06 • 2 DQg DQg DQg DQg DQc DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQh DQd DQd DQd DQd 3 A Bc Bh VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 Bg Bd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A NC NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A www.DataSheet.co.kr 6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD MCL A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A 8 E3 Bb Be NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A Bf Ba VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb DQf DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQb DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQe DQe DQe DQe DQe DQg DQg DQg DQg DQg DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQd DQd DQd DQd DQd 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Note: Users of CMOS I/O SigmaRAMs may wish to connect “NC, VREF” and the “NC, CK” pins to VREF (i.e., VDDQ/2) to allow alternate use of future HSTL I/O SigmaRAMs. Rev: 2.01 5/2003 2/30 © 2002, GSI Technology, Inc. Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative. Datasheet pdf - http://www.DataSheet4U.net/ Preliminary GS8170DW36/72C-333/300/250/200 512k x 36 Common I/O—Top View 1 A B C D E F G H J K L M N P R T U V W • 2002.06 • 2 NC NC NC NC DQc DQc DQc DQc DQc CQ2 NC NC NC NC NC DQd DQd DQd DQd 3 A Bc NC VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 NC Bd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A A NC (144M) NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (72M) A A www.DataSheet.co.kr 6 ADV W E1 MCL VDD ZQ EP2 EP3 MCH MCL MCH MCL MCH MCL VDD MCL A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC (36M) A A 8 E3 Bb NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A NC Ba VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQb DQb DQb DQb NC NC NC NC NC CQ1 DQa DQa DQa DQa DQa NC NC NC NC 11 DQb DQb DQb DQb DQb NC NC NC NC CQ1 DQa DQa DQa DQa NC NC NC NC NC NC NC NC NC NC DQc DQc DQc DQc CQ2 NC NC NC NC DQd DQd DQd DQd DQd 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch .


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