GS8170LW36C-300

GS8170LW36/72C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp Features Late Write mode, Pipelined Read mode JEDEC-standard SigmaRAM™ pinout and package 1.8 V +150/–100 mV core power supply 1.8 V CMOS Interface ZQ controlled user-selectable output drive strength Dual Cycle Deselect Burst Read and Write option Fully coherent read and write pipelines Echo Clock outputs track data output drivers Byte write operation (9-bit bytes) 2 user-programmable chip enable inputs IEEE 1149.1 JTAG-compliant Serial Boundary Scan 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package Pin-compatible with future 36Mb, 72Mb, and 144Mb devices 18Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM™ Functional Description 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O SigmaRAM Family Overview GS8170LW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems. Bottom View 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array www.DataSheet.co.kr ΣRAMs are offered in a number of configurations including Late Write, Double Late Write, and Double Data Rate (DDR). The logical differences between the protocols employed by these RAMs mainly involve various approaches to write cueing and data transfer rates. The ΣRAM™ family standard allows a user to...