50-MHz 32-bit RX MCUs
Preliminary Data Sheet
Specifications in this document are tentative and subject to change.
RX210 Group
Renesas MCUs
5...
Description
Preliminary Data Sheet
Specifications in this document are tentative and subject to change.
RX210 Group
Renesas MCUs
50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA, ELC, MPC, RTC, up to 9 comms interfaces; incorporating functions for IEC60730 compliance
R01DS0041EJ0050 Rev.0.50 Apr 15, 2011
Features
■ 32-bit RX CPU core Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle) Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions, ultra-compact code On-chip debugging circuit ■ Low-power design and architecture Operation from a single 1.62- to 5.5-V supply 1.62-V operation available (at up to 20 MHz) Deep software standby mode with RTC remaining usable Four low-power modes ■ On-chip flash memory for code, no wait states 50-MHz operation, 20-ns read cycle No wait states for reading at full CPU speed 128- to 512-Kbyte capacities User code programmable via the SCI Programmable at 1.62 V For instructions and operands ■ On-chip data flash memory Eight Kbytes, reprogrammable up to TBD times Erasing and programming impose no load on the CPU. ■ On-chip SRAM, no wait states 20- to 64-Kbyte size capacities ■ DMA DMACA: Incorporates four channels ...
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