R5F52201BDFL

Preliminary Datasheet Specifications in this document are tentative and subject to change. RX220 Group Renesas MCUs 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, RTC, up to 7 comms channels; incorporating functions for IEC60730 compliance R01DS0130EJ0051 Rev.0.51 May 24, 2012 Features ■ 32-bit RX CPU core  Max. operating frequency: 32 MHz  Capable of 49 DMIPS in operation at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  On-chip debugging circuit ■ Low-power design and architecture  Operation from a single 1.62-V to 5.5-V supply  1.62-V operation available (at up to TBD MHz)  Three low-power modes ■ On-chip flash memory for code, no wait states  32-MHz operation, 31.25-ns read cycle  No wait states for reading at full CPU speed  Up to 256-Kbyte capacity  User code programmable via the SCI  Programmable at 1.62 V  For instructions and operands ■ On-chip data flash memory  8 Kbytes (Number of times of reprogramming: 100,000)  Erasing and programming impose no load on the CPU. ■ On-chip SRAM, no wait states  Up to 16-Kbyte size capacity ■ DMA  DMAC: Incorporates four channels  DTC: Four transfer modes ■ ELC  Module operation can be i...