Document
2 MHz Non-Synchronous SEPIC/Boost Controller
NCV898031
The NCV898031 is an adjustable output non−synchronous 2 MHz SEPIC/boost controller which drives an external N−channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver.
Protection features include internally−set soft−start, undervoltage lockout, cycle−by−cycle current limiting and thermal shutdown.
Additional features include low quiescent current sleep mode and microprocessor compatible enable pin.
Features
• Peak Current Mode Control with Internal Slope Compensation • 1.2 V $2% Reference Voltage • 2 MHz Fixed Frequency Operation • Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump • Input Undervoltage Lockout (UVLO) • Internal Soft−Start • Low Quiescent Current in Sleep Mode (< 10 mA Typical) • Cycle−by−Cycle Current Limit Protection • Hiccup−Mode Overcurrent Protection (OCP) • Hiccup−Mode Short−Circuit Protection (SCP) • Thermal Shutdown (TSD) • NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
• This is a Pb−Free Device
Typical Applications
• Small Form Factor Point−of−Load Power Regulation • Headlamps • Backlighting
DATA SHEET www.onsemi.com
8 1
SOIC−8 D SUFFIX CASE 751
MARKINGDIAGRAM
8
898031G ALYW G
1
898031G = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
EN 1 ISNS 2 GND 3 GDRV 4
8 VFB 7 VC 6 VIN 5 VDRV
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV898031D1R2G SOIC−8 2500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
1
November, 2021 − Rev. 17
Publication Order Number: NCV898031/D
NCV898031
ENABLE 1
EN
VC 7 RC
CC
TEMP
OSC SC
PWN
FAULT LOGIC
CLK DRIVE LOGIC
VDRV
CL
CSA
+
SCP
Gm SS
Vref
6 VIN
CDRV 5 VDRV
4 GDRV
L1
● CCPL
D
Q
●
L2
2 ISNS 3 GND
RSNS
RF1 8 VFB
RF2
Figure 1. Simplified Block Diagram and Application Schematic
Vg Cg
Vo
Co
PACKAGE PIN DESCRIPTIONS
Pin No.
Pin Symbol
Function
1
EN
Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enable
time−out period.
2
ISNS
Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
3
GND
Ground reference.
4
GDRV
Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance.
5
VDRV
Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0 mF ceramic capacitor to grou.