SST39SF010A. 39SF010A Datasheet

39SF010A SST39SF010A. Datasheet pdf. Equivalent

Part 39SF010A
Description SST39SF010A
Feature 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39SF010A / SST39SF020A / SST39SF040 SST39SF010A.
Manufacture SST
Download 39SF010A Datasheet

1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
SST39SF010A / 020A / 0405.0V 4Mb (x8) MPF memories
Preliminary Specification
• Organized as 128K x8 / 256K x8 / 512K x8
• Single 5.0V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 10 mA (typical)
Standby Current: 30 µA (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Fast Read Access Time:
45 and 70 ns
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:
2 seconds (typical) for SST39SF010A
4 seconds (typical) for SST39SF020A
8 seconds (typical) for SST39SF040
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
TTL I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-pin PLCC
32-pin TSOP (8mm x 14mm)
32-pin PDIP
The SST39SF010A/020A/040 are CMOS Multi-Purpose
Flash (MPF) manufactured with SSTs proprietary, high
performance CMOS SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. The SST39SF010A/020A/040 devices write
(Program or Erase) with a 5.0V power supply. The
SST39SF010A/020A/040 devices conform to JEDEC stan-
dard pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF010A/020A/040 devices provide a maximum
Byte-Program time of 20 µsec. These devices use Toggle
Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, they have
on-chip hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF010A/020A/040 devices are suited for appli-
cations that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, they significantly improve performance and
reliability, while lowering power consumption. They inher-
ently use less energy during erase and program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF010A/020A/040 are offered in 32-pin PLCC and
32-pin TSOP packages. A 600 mil, 32-pin PDIP is also
available. See Figures 1, 2, and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
©2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Datasheet pdf -

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Preliminary Specification
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector-
Erase operation will be ignored.
The Read operation of the SST39SF010A/020A/040 is
controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when either CE# or
OE# is high. Refer to the Read cycle timing diagram (Fig-
ure 4) for further details.
Byte-Program Operation
The SST39SF010A/020A/040 are programmed on a byte-
by-byte basis. Before programming, one must ensure that
the sector, in which the byte which is being programmed
exists, is fully erased.The Program operation consists of
three steps. The first step is the three-byte-load sequence
for Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program
operation, the addresses are latched on the falling edge of
either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever
occurs first. The third step is the internal Program operation
which is initiated after the rising edge of the fourth WE# or
CE#, whichever occurs first. The Program operation, once
initiated, will be completed, within 20 µs. See Figures 5 and
6 for WE# and CE# controlled Program operation timing
diagrams and Figure 15 for flowcharts. During the Program
operation, the only valid reads are Data# Polling and Tog-
gle Bit. During the internal Program operation, the host is
free to perform additional tasks. Any commands written
during the internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte-com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The sector address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising edge of the sixth WE# pulse. The
internal Erase operation begins after the sixth WE# pulse.
The End-of-Erase can be determined using either Data#
Chip-Erase Operation
The SST39SF010A/020A/040 provide Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the 1sstate. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, and Figure 18 for
the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
Write Operation Status Detection
The SST39SF010A/020A/040 provide two software means
to detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system Write cycle time. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE# which ini-
tiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ7)
When the SST39SF010A/020A/040 are in the internal Pro-
gram operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program operation
is completed, DQ7 will produce true data. The device is
then ready for the next operation. During internal Erase
operation, any attempt to read DQ7 will produce a 0. Once
the internal Erase operation is completed, DQ7 will produce
a 1. The Data# Polling is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sec-
©2001 Silicon Storage Technology, Inc.
S71147-02-000 5/01 398
Datasheet pdf -

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