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AD9525 Dataheets PDF



Part Number AD9525
Manufacturers Analog Devices
Logo Analog Devices
Description Low Jitter Clock Generator
Datasheet AD9525 DatasheetAD9525 Datasheet (PDF)

Data Sheet FEATURES Integrated ultralow noise synthesizer 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs 2 differential reference inputs and 1 single-ended reference input APPLICATIONS LTE and multicarrier GSM base stations Clocking high speed ADCs, DACs ATE and high performance instrumentation 40/100 Gb/sec OTN line side clocking Cable/DOCSIS CMTS clocking Test and measurement GENERAL DESCRIPTION The AD9525 is designed to support converter clock requiremen.

  AD9525   AD9525


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Data Sheet FEATURES Integrated ultralow noise synthesizer 8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC output or 2 CMOS SYNC outputs 2 differential reference inputs and 1 single-ended reference input APPLICATIONS LTE and multicarrier GSM base stations Clocking high speed ADCs, DACs ATE and high performance instrumentation 40/100 Gb/sec OTN line side clocking Cable/DOCSIS CMTS clocking Test and measurement GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6. Low Jitter Clock Generator with Eight LVPECL Outputs AD9525 REFA REFA REFB REFB REFC CLKIN .


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