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AN720

Silicon Laboratories

OPTIMIZATION CONSIDERATIONS

AN720 P RECISION 32™ O P T I MI Z A T I O N C ONSIDERATIONS FOR C ODE S I Z E AND S PEED 1. Introduction The code size a...



AN720

Silicon Laboratories


Octopart Stock #: O-724431

Findchips Stock #: 724431-F

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AN720 P RECISION 32™ O P T I MI Z A T I O N C ONSIDERATIONS FOR C ODE S I Z E AND S PEED 1. Introduction The code size and execution speed of a 32-bit MCU project can vary greatly depending on the way the code is written, the toolchain libraries used, and the compiler and linker options. This document addresses how to determine what portions of code are taking extra space or time and ways to optimize for space or speed for different tool chains, including GCC redlib and newlib (Precision32 IDE) and Keil. 2. Key Points The key topics of this document are: How to determine what portions of the project are taking the most space Ways to benchmark code execution speed Common strategies to reduce code size or improve execution speed Code startup time and ways to reduce it 3. Using CoreMark™ as a Speed Benchmark CoreMark is a standard code base that can be ported to various processors to provide a speed benchmark. The CoreMark software provides a score that rates how fast the core and code is, providing a relative comparison between various toolchain options and settings. The CoreMark software package cannot be modified except for device-specific information in the portme files. For modes that do not support printf (nohosting libraries), the results were calculated using the value of the variable in code. See the CoreMark website for more information on the test and score reporting requirements (www.coremark.org). www.DataSheet.net/ 4. Non-Toolchain Considerations The co...




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