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IS46R16160D Dataheets PDF



Part Number IS46R16160D
Manufacturers ISSI
Logo ISSI
Description DDR SDRAM
Datasheet IS46R16160D DatasheetIS46R16160D Datasheet (PDF)

IS43R83200D IS43/46R16160D, IS43/46R32800D JUNE 2012 8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitio.

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IS43R83200D IS43/46R16160D, IS43/46R32800D JUNE 2012 8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe • Burst Length: 2, 4 and 8 • Burst Type: Sequential and Interleave mode • Programmable CAS latency: 2, 2.5 and 3 • Auto Refresh and Self Refresh Modes • Auto Precharge • TRAS Lockout supported (tRAP = tRCD) DEVICE OVERVIEW ISSI’s 256-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 8-bit, 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible. ADDRESS TABLE Parameter Configuration www.DataSheet.net/ 8M x 32 2M x 32 x 4 banks BA0, BA1 16M x 16 4M x 16 x 4 banks BA0, BA1 A10/AP 32M x 8 8M x 8 x 4 banks BA0, BA1 A10/AP Bank Address Pins Autoprecharge A8/AP Pins Row Address Column Address 4K(A0 – A11) 512(A0 – A7, A9) OPTIONS • • • • 8K(A0 – A12) 8K(A0 – A12) 512(A0 – A8) 8K / 64ms 8K / 16ms 1K(A0 – A9) 8K / 64ms Configuration(s): 8Mx32, 16Mx16, 32Mx8 Package(s): 144 Ball BGA (x32) 66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16) Lead-free package available Temperature Range: Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Automotive, A1 (-40°C to +85°C) Automotive, A2 (-40°C to +105°C) Refresh Count Com./Ind./A1 4K / 64ms A2 4K / 16ms KEY TIMING PARAMETERS Speed Grade Fck Max CL = 3 Fck Max CL = 2.5 Fck Max CL = 2 -5 200 200 133 -6 Units 167 167 133 MHz MHz MHz Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 1 Datasheet pdf - http://www.DataSheet4U.co.kr/ IS43R83200D IS43/46R16160D, IS43/46R32800D FUNCTIONAL BLOCK DIAGRAM (x32) CK CK CKE CS RAS CAS WE COMMAND DECODER & CLOCK GENERATOR Mode Registers and Ext. Mode Registers DATA IN BUFFER 32 32 4 DM0-DM3 REFRESH CONTROLLER I/O 0-31 4 DQS0-DQS3 SELF REFRESH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 14 CONTROLLER 32 DATA OUT BUFFER VDD/VDDQ Vss/VssQ 32 REFRESH COUNTER 2 4096 4096 4096 4096 12 ROW DECODER MULTIPLEXER 12 MEMORY CELL ARRAY 12 ROW ADDRESS LATCH 12 12 ROW ADDRESS BUFFER BANK 0 SENSE AMP I/O GATE 2 COLUMN ADDRESS LATCH 9 512 (x 32) BANK CONTROL LOGIC BURST COUNTER www.DataSheet.net/ COLUMN ADDRESS BUFFER COLUMN DECODER 9 2 Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 Datasheet pdf - http://www.DataSheet4U.co.kr/ IS43R83200D IS43/46R16160D, IS43/46R32800D FUNCTIONAL BLOCK DIAGRAM (x16) CK CK CKE CS RAS CAS WE COMMAND DECODER & CLOCK GENERATOR Mode Registers and Ext. Mode Registers DATA IN BUFFER 16 16 2 LDM, UDM REFRESH CONTROLLER I/O 0-15 2 .


IS43R16160D IS46R16160D IS43R32800D


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