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Synchronous DRAM. HY57V28420BT Datasheet

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Synchronous DRAM. HY57V28420BT Datasheet






HY57V28420BT DRAM. Datasheet pdf. Equivalent




HY57V28420BT DRAM. Datasheet pdf. Equivalent





Part

HY57V28420BT

Description

4Banks x 8M x 4bits Synchronous DRAM



Feature


HY57V28420B(L)T 4Banks x 8M x 4bits Sync hronous DRAM DESCRIPTION Preliminary T he Hynix HY57V28420B(L)T is a 134,217,7 28bit CMOS Synchronous DRAM, ideally su ited for the main memory applications w hich require large memory density and h igh bandwidth. HY57V28420B(L)T is organ ized as 4banks of 8,388,608x4. HY57V284 20B(L)T is offering fully synchronous o peration reference.
Manufacture

Hynix

Datasheet
Download HY57V28420BT Datasheet


Hynix HY57V28420BT

HY57V28420BT; d to a positive edge of the clock. All i nputs and outputs are synchronized with the rising edge of the clock input. Th e data paths are internally pipelined t o achieve very high bandwidth. All inpu t and output voltage levels are compati ble with LVTTL. Programmable options in clude the length of pipeline (Read late ncy of 2 or 3), the number of consecuti ve read or write c.


Hynix HY57V28420BT

ycles initiated by a single control comm and (Burst length of 1,2,4,8 or full pa ge), and the burst count sequence(seque ntial or interleave). A burst of read o r write cycles in progress can be termi nated by a burst terminate command or c an be interrupted and replaced by a new burst read or write command on any cyc le. (This pipelined design is not restr icted by a `2N` ru.


Hynix HY57V28420BT

le.) FEATURES • • • Single 3.3±0 .3V power supply All device pins are co mpatible with LVTTL interface JEDEC sta ndard 400mil 54pin TSOP-II with 0.8mm o f pin pitch All inputs and outputs refe renced to positive edge of system clock Data mask function by DQM Internal fou r banks operation • http://www.DataSh eet4U.net/ • • • Auto refresh a nd self refresh 4096 refresh cycl.

Part

HY57V28420BT

Description

4Banks x 8M x 4bits Synchronous DRAM



Feature


HY57V28420B(L)T 4Banks x 8M x 4bits Sync hronous DRAM DESCRIPTION Preliminary T he Hynix HY57V28420B(L)T is a 134,217,7 28bit CMOS Synchronous DRAM, ideally su ited for the main memory applications w hich require large memory density and h igh bandwidth. HY57V28420B(L)T is organ ized as 4banks of 8,388,608x4. HY57V284 20B(L)T is offering fully synchronous o peration reference.
Manufacture

Hynix

Datasheet
Download HY57V28420BT Datasheet




 HY57V28420BT
DESCRIPTION
HY57V28420B(L)T
4Banks x 8M x 4bits Synchronous DRAM
Preliminary
The Hynix HY57V28420B(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory
applications which require large memory density and high bandwidth. HY57V28420B(L)T is organized as 4banks of
8,388,608x4.
HY57V28420B(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by DQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clockshttp://www.DataSheet4U.net/
ORDERING INFORMATION
Part No.
HY57V28420BT-6
HY57V28420BT-K
HY57V28420BT-H
HY57V28420BT-8
HY57V28420BT-P
HY57V28420BT-S
HY57V28420BLT-6
HY57V28420BLT-K
HY57V28420BLT-H
HY57V28420BLT-8
HY57V28420BLT-P
HY57V28420BLT-S
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power Organization
Normal
4Banks x 8Mbits
x4
Low power
Interface
LVTTL
Package
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Nov. 01
datasheet pdf - http://www.DataSheet4U.net/




 HY57V28420BT
PIN CONFIGURATION
HY57V28420B(L)T
PIN DESCRIPTION
VDD 1
54 VSS
NC 2
53 NC
VDDQ 3
52 VSSQ
NC 4
51 NC
DQ0 5
50 DQ3
VSSQ 6
49 VDDQ
NC 7
48 NC
NC 8
47 NC
VDDQ 9
46 VSSQ
NC 10
45 NC
DQ1 11
44 DQ2
VSSQ 12
43 VDDQ
NC 13 54pin TSOP II 42 NC
VDD 14 400mil x 875mil 41 VSS
NC 15 0.8mm pin pitch 40 NC
/WE 16
39 DQM
/CAS 17
38 CLK
/RAS 18
37 CKE
/CS 19
36 NC
BA0 20
35 A11
BA1 21
34 A9
A10/AP 22
33 A8
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VDD 27
28 VSS
http://www.DataSheet4U.net/
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
DQM
DQ0 ~ DQ3
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9,CA11
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.1/Nov. 01
3
datasheet pdf - http://www.DataSheet4U.net/




 HY57V28420BT
FUNCTIONAL BLOCK DIAGRAM
8Mbit x 4banks x 4 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
HY57V28420B(L)T
CLK
CKE
CS
RAS
CAS
WE
DQM
Row active
Row
Pre
Decoders
refresh
Column
Active
Column
Pre
Decoders
Bank Select
Column Add
Counter
8Mx4 Bank3
8Mx4 Bank 2
8Mx4 Bank 1
8Mx4 Bank 0
Memory
Cell
Array
http://www.DataSheet4U.net/
Y decoders
A0 Address
A1 Registers
Burst
Counter
DQ0
DQ1
DQ2
DQ3
A11
BA0
BA1
Mode Registers
CAS Latency
Data Out Control Pipe Line Control
Rev. 0.1/Nov. 01
4
datasheet pdf - http://www.DataSheet4U.net/






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