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CMOS EEPROM. IS34C02B Datasheet

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CMOS EEPROM. IS34C02B Datasheet






IS34C02B EEPROM. Datasheet pdf. Equivalent




IS34C02B EEPROM. Datasheet pdf. Equivalent





Part

IS34C02B

Description

2K-bit 2-WIRE SERIAL CMOS EEPROM



Feature


IS34C02B 2K-bit 2-WIRE SERIAL CMOS EEPRO M with Permanent and Reversible Write-P rotection ISSI ADVANCED INFORMATION AP RIL 2006 ® FEATURES • Two-Wire Ser ial Interface, I C 2 TM DESCRIPTION co mpatible The IS34C02B is an electricall y erasable PROM device that uses the in dustry-standard I2C communication proto col. The IS34C02B contains a non-volati le memory array of 2,.
Manufacture

ISSI

Datasheet
Download IS34C02B Datasheet


ISSI IS34C02B

IS34C02B; 048-bits (256K x 8 bytes), and is furthe r subdivided into 16 pages of 16 bytes each for Pagewrite mode. The device ope rates over the voltage range of 1.7V to 3.6V to satisfy the voltage requiremen ts of DDR2, DDR1, and many other specif ications. In normal Read or Write opera tions, a master device communicates wit h the EEPROM via the two wires Serial C lock and Serial Da.


ISSI IS34C02B

ta. During application system boot-up, i t may be necessary to read out the cont ents of the IS34C02B that pertain to th e configuration of a DRAM module. If th e module manufacturer wishes to safegua rd this memory content, the first half of the array can be write-protected wit h either a permanent or reversible soft ware command, or the entire array can b e writeprotected w.


ISSI IS34C02B

ith the WP input pin. The IS34C02B has t hree address pins, allowing up to eight devices (or memory modules) to be uniq uely accessible in a system. To minimiz e board real-estate, IS34C02B is availa ble in two space-saving packages: TSSOP (8), and DFN(8). All these features mak e the device ideal for use as a Serial Presence Detect (SPD) EEPROM in various types of memory m.

Part

IS34C02B

Description

2K-bit 2-WIRE SERIAL CMOS EEPROM



Feature


IS34C02B 2K-bit 2-WIRE SERIAL CMOS EEPRO M with Permanent and Reversible Write-P rotection ISSI ADVANCED INFORMATION AP RIL 2006 ® FEATURES • Two-Wire Ser ial Interface, I C 2 TM DESCRIPTION co mpatible The IS34C02B is an electricall y erasable PROM device that uses the in dustry-standard I2C communication proto col. The IS34C02B contains a non-volati le memory array of 2,.
Manufacture

ISSI

Datasheet
Download IS34C02B Datasheet




 IS34C02B
IS34C02B
ISSI®
2K-bit 2-WIRE SERIAL CMOS EEPROM
with Permanent and Reversible Write-Protection
ADVANCED INFORMATION
APRIL 2006
FEATURES
• Two-Wire Serial Interface, I2CTM compatible
– Bidirectional data transfer protocol
– 400 kHz (2.5V) and 100 KHz (1.7V) compat-
ibility
• Organization:
– 256 x 8-bit
• Data Protection Features
– Write Protect Pin
– Permanent Software Protection
– Reversible Software Protection
• 16-Byte Page Write Buffer
– Partial Page-writes permitted
• Low Power CMOS Technology
– Active Current less than 3 mA (3.6V)
– Standby Current less than 1 µA (1.7V)
– Standby Current less than 2 µA (3.6V)
• Low Voltage Operation
– IS34C02B-2: Vcc = 1.7V to 3.6V
• Random or Sequential Read Modes
• Filtered Inputs for Noise Suppression
• Self timed Write cycle (5ms max.)
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 40 Years
• Industrial temperature range
• 8-pin TSSOP and DFN (leadless array)
• Lead-free available
DESCRIPTION
The IS34C02B is an electrically erasable PROM device
that uses the industry-standard I2C communication
protocol. The IS34C02B contains a non-volatile memory
array of 2,048-bits (256K x 8 bytes), and is further
subdivided into 16 pages of 16 bytes each for Page-
write mode. The device operates over the voltage range
of 1.7V to 3.6V to satisfy the voltage requirements of
DDR2, DDR1, and many other specifications. In normal
Read or Write operations, a master device communi-
cates with the EEPROM via the two wires Serial Clock
and Serial Data. During application system boot-up, it
may be necessary to read out the contents of the
IS34C02B that pertain to the configuration of a DRAM
module. If the module manufacturer wishes to safe-
guard this memory content, the first half of the array can
be write-protected with either a permanent or reversible
software command, or the entire array can be write-
protected with the WP input pin. The IS34C02B hashttp://www.DataSheet4U.net/
three address pins, allowing up to eight devices (or
memory modules) to be uniquely accessible in a sys-
tem. To minimize board real-estate, IS34C02B is
available in two space-saving packages: TSSOP(8), and
DFN(8). All these features make the device ideal for
use as a Serial Presence Detect (SPD) EEPROM in
various types of memory modules.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published
information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev.00D
03/21/06
1
datasheet pdf - http://www.DataSheet4U.net/




 IS34C02B
IS34C02B
FUNCTIONAL BLOCK DIAGRAM
Vcc
SDA
SCL
WP
A0
A1
A2
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
WORD ADDRESS
COUNTER
GND
nMOS
ACK
http://www.DataSheet4U.net/
ISSI ®
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
00H-7FH
ARRAY
80H-FFH
Y
DECODER
Clock
DI/O
> DATA
REGISTER
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev. 00D
03/21/06
datasheet pdf - http://www.DataSheet4U.net/




 IS34C02B
IS34C02B
PIN CONFIGURATION
8-Pin TSSOP
8-pad DFN
ISSI ®
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
PIN DESCRIPTIONS
WP
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software write-
protection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection
command, the memory in the range of 00h-7Fh is read -only
http://www.DataSheet4U.net/
regardless of the setting of the WP pin.
DEVICE OPERATION
The IS34C02B features a serial communication and supports
a bi-directional 2-wire bus transmission protocol called
I2CTM.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain or
open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
A0, A1, A2
The A0, A1, and A2 are the device address inputs that are
hardwired or left unconnected for hardware flexibility. When
pins are hardwired, as many as eight devices may be
addressed on a single bus system. When the pins are not
hardwired, the default values of A0, A1, and A2 are zero.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving device as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS34C02B is the Slave device on the bus.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
ADVANCED INFORMATION Rev.00D
03/21/06
3
datasheet pdf - http://www.DataSheet4U.net/



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