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Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167
165-Bump BGA Commercial Temp Industrial Temp Features
• Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available • Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices
36Mb SigmaCIO DDR-II Burst of 2 SRAM
167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O
Bottom View
165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.
SigmaCIO™ Family Overview
The GS8342T08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342T08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
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Clocking and Addressing Schemes
The GS8342T08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended
Common I/O x36 and x18 SigmaCIO DDR-II B2 RAMs always transfer data in two packets. When a new address is loaded, A0 presets an internal 1 bit address counter. The counter increments by 1 (toggles) for each beat of a burst of two data transfer. Common I/O x8 SigmaCIO DDR-II B2 RAMs always transfer data in two packets. When a new address is loaded, the LSB is internally set to 0 for the first read or write transfer, and incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always one address pin less than the advertised index depth (e.g., the 8M x 8 has a 2M addressable index).
Parameter Synopsis
-333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -267* 3.75 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns
* The 267 MHz speed bin is only available on the x18 part. Rev: 1.02 8/2005 1/37 © 2003, GSI Technology
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Specifications cited are subject to change without notice. For latest docum.