128K X 8 BIT LOW POWER CMOS SRAM
February 2007
®
AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Ac cess time :55ns Low p owe r consumption: Operat...
Description
February 2007
®
AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Ac cess time :55ns Low p owe r consumption: Operating current:10 mA (TYP.) Standby current: 1 µA (TYP .) Single 2.7V ~ 5.5V po we r supply Fully Compatible with all Competitors 5V product Fully Compatible with all Competitors 3.3V product Fully s tatic operation Tri-state outp ut Data retentio n voltage : 1.5V (MIN.) All products are ROHS Compliant Package : 32-pin 450 mil SOP 32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm sTSOP 36-ball 6mm x 8mm TFBGA
GENERAL DESCRIPTION
The AS6C1008 is a 1,048,576 -bit low powe r CMOS static random access me mory organized as 131,072 words b y 8 bits . It is fabricated using ve ry high performance, high reliability CMOS technolo gy. Its sta ndby current is stable within the ra nge of operating temperature. The AS6C1008 is well designed for very low power system applications, a nd particula rly well suited fo r battery back-u p non-volatile memory a pplication. The AS6C1008 operates from a single power supply of 2.7V ~ 5.5V. .
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FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION Addres s Inputs Da ta Inputs /Outputs Chip Enable Inputs Write Enable Input Output Enable Input Pow er Supply G round No C onnection A0 - A16 DQ0 – DQ7 CE#, CE2 WE# OE# VCC V SS NC
Vcc Vss
A0-A16
DECODER
128Kx8 MEMORY ARRAY
DQ0-DQ7
I/O DATA CIRCUIT
COLUMN I/O
CE# CE2 WE# OE#
CONTROL CIRCUIT
02/February/07, v 1.0
Alliance Memory In...
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