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H5TC4G83AFR-xxI Dataheets PDF



Part Number H5TC4G83AFR-xxI
Manufacturers SK Hynix
Logo SK Hynix
Description 4Gb DDR3L SDRAM
Datasheet H5TC4G83AFR-xxI DatasheetH5TC4G83AFR-xxI Datasheet (PDF)

4Gb DDR3L SDRAM 4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC4G83AFR-xxA H5TC4G83AFR-xxI H5TC4G83AFR-xxL http://www.DataSheet4U.com/ H5TC4G83AFR-xxJ H5TC4G63AFR-xxA H5TC4G63AFR-xxI H5TC4G63AFR-xxL H5TC4G63AFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1 / Jan. 2013 1 Revision History Revision No. 1.0 1.1 History Official Version Release x8 IDD update Draft Date Oct. 2012 Jan. 2013 Remark http://www.DataSheet4U.com/ Rev. 1.1.

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4Gb DDR3L SDRAM 4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC4G83AFR-xxA H5TC4G83AFR-xxI H5TC4G83AFR-xxL http://www.DataSheet4U.com/ H5TC4G83AFR-xxJ H5TC4G63AFR-xxA H5TC4G63AFR-xxI H5TC4G63AFR-xxL H5TC4G63AFR-xxJ * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1 / Jan. 2013 1 Revision History Revision No. 1.0 1.1 History Official Version Release x8 IDD update Draft Date Oct. 2012 Jan. 2013 Remark http://www.DataSheet4U.com/ Rev. 1.1 / Jan. 2013 2 Description The H5TC4G83AFR-xxA(I,L,J) and H5TC4G63AFR-xxA(I,L,J) are a 4Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 4Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 and 11, 13 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 85 oC) Industrial Temperature( -40oC ~ 95 oC) http://www.DataSheet4U.com/ • JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16) Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 1.1 / Jan. 2013 3 ORDERING INFORMATION Part No. H5TC4G83AFR-*xxA H5TC4G83AFR-*xxI H5TC4G83AFR-*xxL H5TC4G83AFR-*xxJ H5TC4G63AFR-*xxA H5TC4G63AFR-*xxI H5TC4G63AFR-*xxL H5TC4G63AFR-*xxJ 256M x 16 Low Power Consumption (IDD6 Only) 512M x 8 Low Power Consumption (IDD6 Only) Normal Consumption Configuration Power Consumption Normal Consumption Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 96ball FBGA 78ball FBGA Package * xx means Speed Bin Grade OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 -PB -RD Frequency [MHz] CL5 667 667 667 CL6 800 800 800 800 CL7 1066 1066 1066 1066 CL8 1066 1066 1066 1066 1333 1333 1333 1333 1333 1333 1600 1600 1866 CL9 CL10 http://www.DataSheet4U.com/ CL11 CL12 CL13 CL14 Remark (CL-tRCD-tRP) DDR3L-1066 7-7-7 DDR3L-1333 9-9-9 DDR3L-1600 11-11-11 DDR3L-1866 13-13-13 Rev. 1.1 / Jan. 2013 4 x8 Package Ball out (Top view): 78ball FBGA Package 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NF/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP A15 A12/BC A1 A11 A14 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 1 2 3 A B C D E F G H J K L M N 7 8 9 http://www.DataSheet4U.com/ (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.1 / Jan. 2013 5 x16 Package Ball out (Top view): 96ball FBGA Package 1 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP NC A12/BC A1 A11 A14 7 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N P R T http://www.DataSheet4U.com/ 1 2 3 A B C D E F G H J K L M N P R T 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.1 / Jan. 2013 6 Pin Functional Description Symbol CK, CK Type Input Function Clock: CK and CK are differential clock inputs. All address a.


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