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H5TC2G43AFR-xxA Dataheets PDF



Part Number H5TC2G43AFR-xxA
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 2Gb DDR3L SDRAM
Datasheet H5TC2G43AFR-xxA DatasheetH5TC2G43AFR-xxA Datasheet (PDF)

2Gb DDR3L SDRAM 2Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC2G43AFR-xxA H5TC2G83AFR-xxA http://www.DataSheet4U.com/ * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.1 / Nov. 2009 1 Revision History Revision No. 0.1 History Initial Release Draft Date Nov. 2009 Remark Preliminary http://www.DataSheet4U.com/ Rev. 0.1 / Nov. 2009 2 Description The H5TC2G43AFR-xxA, H5TC2G83AFR-xxA are a 2Gb low power Double Data Rate III (DDR.

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2Gb DDR3L SDRAM 2Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC2G43AFR-xxA H5TC2G83AFR-xxA http://www.DataSheet4U.com/ * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 0.1 / Nov. 2009 1 Revision History Revision No. 0.1 History Initial Release Draft Date Nov. 2009 Remark Preliminary http://www.DataSheet4U.com/ Rev. 0.1 / Nov. 2009 2 Description The H5TC2G43AFR-xxA, H5TC2G83AFR-xxA are a 2Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.35V. Hynix DDR3L SDRAM provides backward compatibility with the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.) Hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.35V + 0.100 / - 0.067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 and (11) supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC • Auto Self Refresh supported • JEDEC standard 82ball FBGA(x4/x8) • Driver strength selected by EMRS http://www.DataSheet4U.com/ • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 0.1 / Nov. 2009 3 ORDERING INFORMATION Part No. H5TC2G43AFR-*xxA H5TC2G83AFR-*xxA Configuration 512M x 4 256M x 8 Package 82ball FBGA OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 Frequency [MHz] CL5 CL6 O O CL7 O O CL8 O O O O CL9 CL10 CL11 Remark (CL-tRCD-tRP) DDR3L-1066 7-7-7 DDR3L-1333 9-9-9 * xx means Speed Bin Grade http://www.DataSheet4U.com/ Rev. 0.1 / Nov. 2009 4 Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 82ball FBGA Package 1 A B C D E F G H J K L M N NC 1 NC 2 VSS VSS VDDQ VSSQ VREFDQ NC ODT .


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