Document
K7A403600M
Document Title
128Kx36-Bit Synchronous Pipelined Burst SRAM
128Kx36 Synchronous SRAM
Revision History
Rev. No. 0.0 0.1 0.2 0.3 History Initial draft Change 7.5 bin to 7.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85 Draft Date May . 15. 1997 January . 13 . 1998 February. 02. 1998 Remark Preliminary Preliminary Preliminary Preliminary
Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change February. 12. 1998 Input/output leackage currant for ±1µA to ±2µA Modify Read timing & Power down cycle timing. Change ISB2 value from 30mA to 20mA. Remove DC characteristics ISB1 - L ver.& ISB2 - L ver . Remove Low power version. Add 119BGA(7x17 Ball Grid Array Package) Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.6V((pulse width≤tCYC/2) Change VIH max from 5.5V to VDD+0.5V March. 11 . 1998
0.4
Preliminary
0.5
April. 14. 1998
Preliminary
0.6
May.13. 1998 Change ISB2 value from 20mA to 30mA. Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
http://www.DataSheet4U.com/
Preliminary
0.7
Modify DC characteristics( Input Leakage Current test Conditions) form VDD=VSS to VDD to Max. Final spec Release Add VDDQ Supply voltage( 2.5V ) Remove 119BGA(7x17 Ball Grid Array Package) .
May.14.1998
Preliminary
1.0 2.0 3.0
May. 15. 1998 Dec. 02. 1998 Nov. 26. 1999
Final Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
November 1999 Rev 3.0
This datasheet has been downloaded from http://www.digchip.com at this page
K7A403600M
128Kx36 Synchronous SRAM
128Kx36-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 3.3V+0.3V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A Package .
GENERAL DESCRIPTION
The K7A403600M is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 128K words of 36bits and integrates address and control registers, a 2.