ADAU1978

Data Sheet Quad Analog-to-Digital Converter (ADC) ADAU1978 FEATURES Four 2 V rms differential inputs On-chip phase-locked loop (PLL) for master clock Low electromagnetic interference (EMI) design 109 dB analog-to-digital converter (ADC) dynamic range Total harmonic distortion + noise (THD + N): −95 dB Selectable digital high-pass filter 24-bit stereo ADC with 8 kHz to 192 kHz sample rates Digital volume control with autoramp function I2C/SPI controllable for flexibility Software-controllable clickless mute Software power-down Right justified, left justified, I2S, and TDM modes Master and slave operation modes 40-lead LFCSP package Qualified for automotive applications APPLICATIONS Automotive audio systems Active noise cancellation systems GENERAL DESCRIPTION The ADAU1978 incorporates four high performance, analog-todigital converters (ADCs) with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3 V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it ...