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FM24C16A
16Kb FRAM Serial Memory Features
16K bit Ferroelectric Nonvolatile RAM • Organized as 2,048 x 8 bits • High Endurance (1012) Read/Write Cycles • 45 year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface • Up to 1MHz maximum bus frequency • Direct hardware replacement for EEPROM Low Power Operation • 5V operation • 150 µA Active Current (100 kHz) • 10 µA Standby Current Industry Standard Configuration • Industrial Temperature -40° C to +85° C • 8-pin SOIC (-S) • “Green” 8-pin SOIC (-G)
Description
The FM24C16A is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for over 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM24C16A performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The FM24C16A is capable of supporting 1012 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24C16A ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows the system to write data more frequently, with less system overhead. The FM24C16A provides substantial benefits to users of serial EEPROM, and these benefits are available as a hardware drop-in replacement. The FM24C16A is available in an industry standard 8-pin SOIC and uses a two-wire protocol. The specifications are guaranteed over the industrial temperature range from -40°C to +85°C.
Pin Configuration
NC NC NC VSS
1 2 3 4 8 7 6 5
VDD WP SCL SDA
Pin Names SDA SCL WP VDD VSS
Function Serial Data/Address Serial Clock Write Protect Supply Voltage 5V Ground
Ordering Information
FM24C16A-S FM24C16A-G 8-pin SOIC “Green” 8-pin SOIC
This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Rev. 3.0 Mar. 2005
Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000
www.ramtron.com
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Free Datasheet http://www.datasheet4u.com/
FM24C16A
Counter
Address Latch
256 x 64 FRAM Array
8
SDA
`
Serial to Parallel Converter
Data Latch
SCL WP Control Logic
Figure 1. Block Diagram
Pin Description Pin Name SDA Type I/O Pin Description Serial Data Address: This is a bi-directional data pin for the two-wire interface. It employs an open-drain output and is intended to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on the falling edge and clocked-in on the rising edge. Write Protect: When WP is high, the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down. Supply Voltage (5V) Ground No connect
SCL WP VDD VSS NC
Input Input Supply Supply -
Rev 3.0 Mar. 2005
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FM24C16A
Overview
The FM24C16A is a serial FRAM memory. The memory array is logically organized as a 2,048 x 8 memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C16A and a serial EEPROM with the same pinout relates to its superior write performance.
Two-wire Interface
The FM24C16A employs a bi-directional two-wire bus protocol using few pins and little board space. Figure 2 illustrates a typical system configuration using the FM24C16A in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24C16A is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including Start, Stop, Data bit, and Acknowledge. Figure 3 illustrates the signal conditions that define the four states. Detailed timing diagrams are shown in the Electrical Specifications section.
Memory Architecture
When accessing the FM24C.