(PDF) DP83640 Datasheet PDF | National Semiconductor





DP83640 Datasheet PDF

Part Number DP83640
Description Precision Time Protocol Transceiver
Manufacture National Semiconductor
Total Page 30 Pages
PDF Download Download DP83640 Datasheet PDF

Features: Datasheet pdf DP83640 Precision PHYTER - IEEE 1588 Pre cision Time Protocol Transceiver Febru ary 26, 2008 DP83640 Precision PHYTER - IEEE® 1588 Precision Time Protocol T ransceiver 1.0 General Description The DP83640 Precision PHYTER® device deliv ers the highest level of precision cloc k synchronization for real time industr ial connectivity based on the IEEE 1588 standard. The DP83640 has deterministi c, low latency and allows choice of mic rocontroller with no hardware customiza tion required. The integrated 1588 func tionality allows system designers the f lexibility and precision of a close to the wire timestamp. The three key 1588 features supported by the device are: Packet time stamps for clock synchro nization — Integrated IEEE 1588 synch ronized clock generation — Synchroniz ed event triggering and time stamping t hrough GPIO DP83640 offers innovative d iagnostic features unique to National S emiconductor, including dynamic monitor ing of link quality during standard operation for fault prediction. The.

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DP83640 datasheet
February 26, 2008
DP83640
Precision PHYTER - IEEE® 1588 Precision Time Protocol
Transceiver
1.0 General Description
The DP83640 Precision PHYTER® device delivers the high-
est level of precision clock synchronization for real time in-
dustrial connectivity based on the IEEE 1588 standard. The
DP83640 has deterministic, low latency and allows choice of
microcontroller with no hardware customization required. The
integrated 1588 functionality allows system designers the
flexibility and precision of a close to the wire timestamp. The
three key 1588 features supported by the device are:
— Packet time stamps for clock synchronization
— Integrated IEEE 1588 synchronized clock generation
— Synchronized event triggering and time stamping through
GPIO
DP83640 offers innovative diagnostic features unique to Na-
tional Semiconductor, including dynamic monitoring of link
quality during standard operation for fault prediction. These
advanced features allow the system designer to implement a
fault prediction mechanism to detect and warn of deteriorating
and changing link conditions. This single port fast Ethernet
transceiver can support both copper and fiber media.
2.0 Applications
Factory Automation
Ethernet/IP
CIP Sync
Test and Measurement
LXI Standard
Telecom
Basestation
Real Time Networking
3.0 Features
IEEE 1588 V1 and V2 supported
UDP/IPv4, UDP/IPv6, and Layer2 Ethernet packets
supported
IEEE 1588 clock synchronization
Timestamp resolution of 8 ns
Allows sub 100 ns synchronization to master reference
12 IEEE 1588 GPIOs for trigger or capture
Deterministic, low transmit and receive latency
Selectable frequency synchronized clock output
Dynamic Link Quality monitoring
TDR based Cable Diagnostic and Cable Length Detection
10/100 Mb/s packet BIST (Built in Self Test)
Error-free Operation up to 150 meters CAT5 cable
ESD protection - 8 kV human body model
3.3 V I/Os and MAC interface
Auto-MDIX for 10/100 Mbps
RMII Rev. 1.2 and MII MAC interface
25 MHz MDC and MDIO Serial Management Interface
IEEE 802.3u 100BASE-FX Fiber Interface
IEEE 1149.1 JTAG
Programmable LED support for Link, 10 /100 Mb/s Mode,
Duplex, Activity, and Collision Detect
Optional 100BASE-TX fast link-loss detection
48 pin LQFP package (7mm) x (7mm)
4.0 System Diagram
PHYTER® is a registered trademark of National Semiconductor.
© 2008 National Semiconductor Corporation 300112
30011217
www.national.com
Free Datasheet http://www.datasheet4u.com/

DP83640 datasheet
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
4.0 System Diagram .............................................................................................................................. 1
5.0 Block Diagram ................................................................................................................................ 6
6.0 Key IEEE 1588 Features .................................................................................................................. 6
6.1 IEEE 1588 SYNCHRONIZED CLOCK .............................................................................................. 7
6.1.1 IEEE 1588 Clock Output ............................................................................................................ 7
6.1.2 IEEE 1588 Clock Input .............................................................................................................. 8
6.2 PACKET TIMESTAMPS ................................................................................................................ 8
6.2.1 IEEE 1588 Transmit Packet Parser and Timestamp ....................................................................... 8
6.2.1.1 One-Step Operation ............................................................................................................. 8
6.2.2 IEEE 1588 Receive Packet Parser and Timestamp ....................................................................... 8
6.2.2.1 Receive Timestamp Insertion ................................................................................................. 8
6.2.3 NTP Packet Timestamp ............................................................................................................. 8
6.3 EVENT TRIGGERING AND TIMESTAMPING ................................................................................... 8
6.3.1 IEEE 1588 Event Triggering ....................................................................................................... 8
6.3.2 IEEE 1588 Event Timestamping ................................................................................................. 8
6.4 PTP INTERRUPTS ........................................................................................................................ 8
6.5 GPIO ........................................................................................................................................... 8
7.0 Pin Layout ...................................................................................................................................... 9
8.0 Pin Descriptions ............................................................................................................................ 10
8.1 SERIAL MANAGEMENT INTERFACE ........................................................................................... 10
8.2 MAC DATA INTERFACE .............................................................................................................. 10
8.3 CLOCK INTERFACE ................................................................................................................... 12
8.4 LED INTERFACE ........................................................................................................................ 13
8.5 IEEE 1588 EVENT/TRIGGER/CLOCK INTERFACE ......................................................................... 13
8.6 JTAG INTERFACE ...................................................................................................................... 13
8.7 RESET AND POWER DOWN ....................................................................................................... 14
8.8 STRAP OPTIONS ....................................................................................................................... 15
8.9 10 Mb/s AND 100 Mb/s PMD INTERFACE ...................................................................................... 16
8.10 POWER SUPPLY PINS .............................................................................................................. 17
8.11 PACKAGE PIN ASSIGNMENTS .................................................................................................. 17
9.0 Configuration ................................................................................................................................ 18
9.1 MEDIA CONFIGURATION ............................................................................................................ 18
9.2 AUTO-NEGOTIATION ................................................................................................................. 18
9.2.1 Auto-Negotiation Pin Control .................................................................................................... 18
9.2.2 Auto-Negotiation Register Control ............................................................................................. 18
9.2.3 Auto-Negotiation Parallel Detection ........................................................................................... 19
9.2.4 Auto-Negotiation Restart .......................................................................................................... 19
9.2.5 Enabling Auto-Negotiation via Software ..................................................................................... 19
9.2.6 Auto-Negotiation Complete Time .............................................................................................. 19
9.3 AUTO-MDIX ............................................................................................................................... 19
9.4 PHY ADDRESS .......................................................................................................................... 19
9.4.1 MII Isolate Mode ..................................................................................................................... 19
9.4.2 Broadcast Mode ..................................................................................................................... 20
9.5 LED INTERFACE ........................................................................................................................ 20
9.5.1 LEDs ..................................................................................................................................... 21
9.5.2 LED Direct Control .................................................................................................................. 21
9.6 HALF DUPLEX vs. FULL DUPLEX ................................................................................................ 21
9.7 INTERNAL LOOPBACK ............................................................................................................... 21
9.8 POWER DOWN/INTERRUPT ....................................................................................................... 21
9.8.1 Power Down Control Mode ...................................................................................................... 21
9.8.2 Interrupt Mechanisms .............................................................................................................. 22
9.9 ENERGY DETECT MODE ............................................................................................................ 22
9.10 LINK DIAGNOSTIC CAPABILITIES ............................................................................................. 22
9.10.1 Linked Cable Status .............................................................................................................. 22
9.10.1.1 Polarity Reversal .............................................................................................................. 22
9.10.1.2 Cable Swap Indication ...................................................................................................... 22
9.10.1.3 100 Mb Cable Length Estimation ........................................................................................ 22
9.10.1.4 Frequency Offset Relative to Link Partner ............................................................................ 22
9.10.1.5 Cable Signal Quality Estimation .......................................................................................... 22
9.10.2 Link Quality Monitor ............................................................................................................... 22
9.10.2.1 Link Quality Monitor Control and Status ............................................................................... 23
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