K7A803609A

K7A803609A K7A801809A Document Title 256Kx36 & 512Kx18 Synchronous SRAM 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 1.0 History Initial draft 1. Final spec Release. Draft Date May. 24 . 2000 July. 03. 2000 Remark Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- July 2000 Rev 1.0 Free Datasheet http://www.datasheet4u.com/ K7A803609A K7A801809A 256Kx36 & 512Kx18 Synchronous SRAM 256Kx36 & 512Kx18-bit Synchronous Pipelined Burst SRAM FEATURES Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. 3.3V+0.165V/-0.165V Power Supply. I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O 5V Tolerant Inputs Except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. LBO Pin allows a choice of either a interleaved burst or a linear burst. Three Chip Enables for simple depth expansion with No Data Contention only for TQFP ; 2cycle Enable, 1cycle Disable. Asynchronous Outpu...