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IS61NSCS25672 Dataheets PDF



Part Number IS61NSCS25672
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description Synchronous SRAM
Datasheet IS61NSCS25672 DatasheetIS61NSCS25672 Datasheet (PDF)

IS61NSCS25672 IS61NSCS51236 Σ RAM 256K x 72, 512K x 36 Features • JEDEC SigmaRam pinout and package standard • Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max) • Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical • LVCMOS-compatible I/O interface • Common data I/O pins (DQs) • Single Data Rate (SDR) data transfers • Pipelined (PL) read operations • Double Late Write (DLW) write operations • Burst and non-burst read and write operations, selectable via dedicated control pin (AD.

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IS61NSCS25672 IS61NSCS51236 Σ RAM 256K x 72, 512K x 36 Features • JEDEC SigmaRam pinout and package standard • Single 1.8V power supply (VCC): 1.7V (min) to 1.9V (max) • Dedicated output supply voltage (VCCQ): 1.8V or 1.5V typical • LVCMOS-compatible I/O interface • Common data I/O pins (DQs) • Single Data Rate (SDR) data transfers • Pipelined (PL) read operations • Double Late Write (DLW) write operations • Burst and non-burst read and write operations, selectable via dedicated control pin (ADV) • Internally controlled Linear Burst address sequencing during burst operations • Burst length of 2, 3, or 4, with automatic address wrap • Full read/write coherency • Byte write capability • Two cycle deselect • Single-ended input clock (CLK) • Data-referenced output clocks (CQ/CQ) • Selectable output driver impedance via dedicated control pin (ZQ) • Echo clock outputs track data output drivers • Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3) • JTAG boundary scan (subset of IEEE standard 1149.1) • 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package ISSI ® ADVANCE INFORMATION JUNE 2001 18Mb Synchronous SRAM Bottom View 209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array SigmaRAM Family Overview The IS61NSCS series Σ RAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs. The implementations are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage CMOS I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. ISSI’ s ΣRAMs are offered in a number of configurations that emulate other synchronous SRAMs, such as Burst RAMs, NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering and write cueing. ΣRAMs allow a user to implement the interface protocol best suited to the task at hand. This specific product is Common I/O, SDR, Double Late Write & Pipelined Read (same as Pipelined NBT) and in the family is identified as 1x1Dp. This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 ADVANCE INFORMATION 06/19/01 Rev. 00A 1 Free Datasheet http://www.datasheet4u.com/ IS61NSCS25672 IS61NSCS51236 Functional Description Because SigmaRAM is a synchronous device, address, data Inputs, and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. ISSI ® Single data rate ΣRAMs incorporate a rising-edge-triggered output register. For read cycles, ΣRAM’s output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. IS61NSCS series Σ RAMs are implemented with ISSI’s high performance CMOS technology and are packaged in a 209-bump BGA. IS61NSCS25672 PINOUT 256K x 72 Common I/O—Top View 1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DQPg DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQPd DQd DQd DQd DQd 2 DQg DQg DQg DQg DQPc DQc DQc DQc DQc CQ2 DQh DQh DQh DQh DQPh DQd DQd DQd DQd 3 A Bc Bh GND VCCQ GND VCCQ GND VCCQ CLK VCCQ GND VCCQ GND VCCQ GND NC A TMS 4 E2 Bg Bd NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDI 5 A (16M) NC NC (128M) NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC (64M) A A 6 ADV W E1 MCL VCC ZQ EP2 EP3 M4 MCL M2 M3 SD MCL VCC MCL A A1 A0 7 A (8M) A NC NC VCC GND VCC GND VCC GND VCC GND VCC GND VCC NC NC (32M) A A 8 E3 Bb Be NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ NC A A TDO 9 A Bf Ba GND VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ GND VCCQ GND NC A TCK 10 DQb DQb DQb DQb DQPf DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DQPb DQf DQf DQf DQf CQ1 DQa DQa DQa DQa DQPe DQe DQe DQe DQe 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 ADVANCE INFORMATION Rev. 00A 06/19/01 Free Datasheet http://www.datasheet4u.com/ IS61NSCS25672 IS61NSCS51236 IS61NSCS51236 PINOUT 512K x 36 Common I/O—Top View 1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC DQc DQc DQc DQc CQ2 NC NC NC NC DQPd DQd DQd DQd DQd 2 NC NC NC NC DQPc DQc DQc DQc DQc CQ2 NC NC NC NC NC DQd DQd DQd DQd 3 A Bc NC GND VCCQ GND VCCQ GND VCCQ CLK VCCQ GND VCCQ GND VCCQ GND NC A TMS 4 E2 NC Bd NC VCCQ GND VCCQ GND VCCQ NC VCCQ GND VCCQ G.


SI510 IS61NSCS25672 IS61NSCS51236


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