DDR Termination Regulator
FEATURES
z z z z z z z z Low Output Voltage Offset Works with +5V, +3.3V, and 2.5V Rails Sourc...
DDR Termination
Regulator
FEATURES
z z z z z z z z Low Output Voltage Offset Works with +5V, +3.3V, and 2.5V Rails Source and Sink Current Low External Component Count No External Resistors Required Linear Topology Available in SOP8, SOP8-PP Package Low Cost and Easy to Use SOP8 / SOP8-PP PKG
TJ2995
APPLICATION
z DDR-I and DDR-II Termination Voltage z SSTL-2 and SSTL-3 Termination
ORDERING INFORMATION Device (Marking) TJ2995D TJ2995DP Package SOP8 SOP8-PP
DESCRIPSION
The TJ2995 linear
regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transient. This device can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the TJ2995 can provide superior load regulation. The TJ2995 provides a VREF output as the reference for the chipset and DDR DIMMS. The TJ2995 can easily provide the accurate VTT and VREF voltages without external resistors that PCB areas can be reduced. The quiescent current is low to meet the low power consumption applications.
Absolute Maximum Ratings
CHARACTERISTIC
Supply Voltage to GND Lead Temperature (Soldering, 10 sec) Storage Temperature Range Operating Junction Temperature Range
SYMBOL
PVIN AVIN VDDQ TSOL TSTG TJOPR
MIN.
-0.3 -0.3 -0.3 -65 -40
MAX.
6.0 6.0 6.0 260 150 125
UNIT
V ℃ ℃ ℃
Recommended Operation Ran...