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UPA2761UGR

Renesas

MOS FIELD EFFECT TRANSISTOR

Preliminary Data Sheet μ PA2761UGR MOS FIELD EFFECT TRANSISTOR Description R07DS0010EJ0100 Rev.1.00 Jun 01, 2010 The ...


Renesas

UPA2761UGR

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Description
Preliminary Data Sheet μ PA2761UGR MOS FIELD EFFECT TRANSISTOR Description R07DS0010EJ0100 Rev.1.00 Jun 01, 2010 The μ PA2761UGR is N-Channel MOS Field Effect Transistor designed for power management applications of a notebook computer. Features Low on-state resistance ⎯ RDS(on)1 = 18.5 mΩ MAX. (VGS = 10 V, ID = 9 A) ⎯ RDS(on)2 = 30 mΩ MAX. (VGS = 4.5 V, ID = 7 A) Low Ciss: Ciss = 550 pF TYP. (VDS = 15 V, VGS = 0 V) Small and surface mount package (Power SOP8) RoHS Compliant Ordering Information Part No. μ PA2761UGR-E1-AT ∗1 μ PA2761UGR-E2-AT ∗1 LEAD PLATING Pure Sn (Tin) PACKING Tape 2500 p/reel Package Power SOP8 0.08 g TYP. Note: ∗1. Pb-free (This product does not contain Pb in external electrode and other parts.) Absolute Maximum Ratings (TA = 25°C, All terminals are connected) Item Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) 1 Drain Current (pulse) ∗ 2 Total Power Dissipation ∗ 2 Total Power Dissipation (PW = 10 sec) ∗ Channel Temperature Storage Temperature 3 Single Avalanche Current ∗ ∗3 Single Avalanche Energy Symbol VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg IAS EAS Ratings 30 ±25 ±9 ±40 1.1 2.5 150 −55 to +150 9 8.1 Unit V V A A W W °C °C A mJ Notes: ∗1. PW ≤ 10 μs, Duty Cycle ≤ 1% ∗ 2. Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt ∗ 3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 μH R07DS0010EJ0100 Rev.1.00 Jun 01, 2010 Page 1 of 6 Free Datasheet http://www.da...




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