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H5TQ4G43MFR-xxC Dataheets PDF



Part Number H5TQ4G43MFR-xxC
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4Gb DDR3 SDRAM
Datasheet H5TQ4G43MFR-xxC DatasheetH5TQ4G43MFR-xxC Datasheet (PDF)

4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G43MFR-xxC H5TQ4G83MFR-xxC H5TQ4G63MFR-xxC * SK hyix Semiconductor reserves the right to change products or specifications without Rev. 1.0 / Nov. 2012 1 Free Datasheet http://www.datasheet4u.com/ Revision History Revision No. 0.1 0.2 0.3 0.4 0.5 1.0 History Initial Release Ballout typo correction Package Dimension correction Added IDD Specification Added IDD Specification(x16) Latest JEDEC Spec Updated Draft Date Ap.

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4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ4G43MFR-xxC H5TQ4G83MFR-xxC H5TQ4G63MFR-xxC * SK hyix Semiconductor reserves the right to change products or specifications without Rev. 1.0 / Nov. 2012 1 Free Datasheet http://www.datasheet4u.com/ Revision History Revision No. 0.1 0.2 0.3 0.4 0.5 1.0 History Initial Release Ballout typo correction Package Dimension correction Added IDD Specification Added IDD Specification(x16) Latest JEDEC Spec Updated Draft Date Apr. 2011 May. 2011 Jun. 2011 Aug. 2011 Nov. 2011 Nov. 2012 Remark Rev. 1.0 / Nov. 2012 2 Free Datasheet http://www.datasheet4u.com/ Description The H5TQ4G43MFR-xxC, H5TQC4G83MFR-xxC and H5TQ4G63MFR-xxC are a 4Gb CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V + - 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.8 µs at 0oC ~ 85 oC - 3.9 µs at 85oC ~ 95 oC • On chip DLL align DQ, DQS and DQS transition with CK  • JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16) transition • DM masks write data-in at the both rising and falling  edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 and 11, 13 supported • Programmable additive latency 0, CL-1, and CL-2  supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch • This product in compliance with the RoHS directive. Rev. 1.0 / Nov. 2012 3 Free Datasheet http://www.datasheet4u.com/ ORDERING INFORMATION Part No. H5TQ4G43MFR-*xxC H5TQ4G83MFR-*xxC H5TQ4G63MFR-*xxC Configuration 1G x 4 512M x 8 256Mx16 Package 78ball FBGA 96ball FBGA OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 -PB -RD Frequency [MHz] CL5 O O O O CL6 O O O O CL7 O O O O CL8 O O O O O O O O O O O O O CL9 CL10 CL11 CL12 CL13 Remark (CL-tRCD-tRP) DDR3-1066 7-7-7 DDR3-1333 9-9-9 DDR3-1600 11-11-11 DDR3-1866 13-13-13 * xx means Speed Bin Grade Rev. 1.0 / Nov. 2012 4 Free Datasheet http://www.datasheet4u.com/ Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 78ball FBGA Package 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 NF VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS NF RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NF DM DQ1 VDD NF CK CK A10/AP A15 A12/BC A1 A11 A14 7 8 VSS VSSQ DQ3 VSS NF VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N Note: NF (No Function) - This is applied to balls only used in x4 configuration. 1 2 3 A B C D E F G H J K L M N 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.0 / Nov. 2012 5 Free Datasheet http://www.datasheet4u.com/ x8 Package Ball out (Top view): 78ball FBGA Package 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NF/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP A15 A12/BC A1 A11 A14 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 1 2 3 A B C D E F G H J K L M N 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.0 / Nov. 2012 6 Free Datasheet http://www.datasheet4u.com/ x16 Package Ball out (Top view): 96ball FBGA Package 1 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP NC A12/BC A1 A11 A14 7 8 VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G.


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