Document
240pin DDR3L SDRAM Unbuffered DIMM
DDR3L SDRAM Unbuffered DIMMs Based on 4Gb A-Die
HMT425U6AFR6A HMT451U6AFR8A HMT451U7AFR8A HMT41GU6AFR8A HMT41GU7AFR8A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.1 / Jul. 2013
1
Free Datasheet http://www.datasheet4u.com/
Revision History
Revision No. 0.1 1.0 1.1 History Initial Release Changed module maximum thickness to reflect the measured maximum Collected module dimension Draft Date Jul. 2012 May. 2013 Jul. 2013 Remark
Rev. 1.1 / Jul. 2013
2
Free Datasheet http://www.datasheet4u.com/
Description
SK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual InLine Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations.
Feature
• Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ=1.35V (1.283 to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-12800, PC3-10600, PC3-8500 • Bi-directional Differential Data Strobe • 8 bit pre-fetch • Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4 • Supports ECC error correction and detection • On Die Termination (ODT) supported • Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM • This product is in Compliance with the RoHS directive
Ordering Information
Part Number HMT425U6AFR6A-G7/H9/PB HMT451U6AFR8A-G7/H9/PB HMT451U7AFR8A-G7/H9/PB HMT41GU6AFR8A-G7/H9/PB HMT41GU7AFR8A-G7/H9/PB Density 2GB 4GB 4GB 8GB 8GB Organization 256Mx64 512Mx64 512Mx72 1Gx64 1Gx72 Component Composition 256Mx16(H5TC4G63AFR)*4 512Mx8(H5TC4G83AFR)*8 512Mx8(H5TC4G83AFR)*9 512Mx8(H5TC4G83AFR)*16 512Mx8(H5TC4G83AFR)*18 # of ranks 1 1 1 2 2 FDHS X X X X X
Rev. 1.1 / Jul. 2013
3
Free Datasheet http://www.datasheet4u.com/
Key Parameters
MT/s DDR3L-1066 DDR3L-1333 DDR3L-1600 Grade -G7 -H9 -PB tCK (ns) 1.875 1.5 1.25 CAS Latency (tCK) 7 9 11 tRCD (ns) 13.125 tRP (ns) 13.125 tRAS (ns) 37.5 36 35 tRC (ns) 50.625 49.5 (49.125)* 48.75 (48.125)* CL-tRCD-tRP 7-7-7 9-9-9 11-11-11
13.5 13.5 (13.125)* (13.125)* 13.75 13.75 (13.125)* (13.125)*
*SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz] Grade CL6 -G7 -H9 -PB 800 800 800 CL7 1066 1066 1066 CL8 1066 1066 1066 1333 1333 1333 1333 1600 CL9 CL10 CL11 Remark
Address Table
2GB(1Rx16) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A14 A0-A9 BA0-BA2 2KB 4GB(1Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB 4GB(1Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB 8GB(2Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB 8GB(2Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB
Rev. 1.1 / Jul. 2013
4
Free Datasheet http://www.datasheet4u.com/
Pin Descriptions
Pin Name A0–A15 BA0–BA2 RAS CAS WE S0–S1 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 DM0–D.