Document
240pin DDR3 SDRAM Unbuffered DIMM
DDR3 SDRAM Unbuffered DIMMs Based on 4Gb M-Die
HMT451U6MFR8C HMT41GU6MFR8C HMT41GU7MFR8C
*SK hynix reserves the right to change products or specifications without notice.
Rev.1.1 /Jul. 2013
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Free Datasheet http://www.datasheet4u.com/
Revision History
Revision No. 0.1 0.2 0.3 1.0 1.1 History Initial Release Added 4GB UDIMM JEDEC Spec Updated Module Dimension Updated Changed module maximum thickness to reflect the measured maximum Draft Date Jul. 2011 Sep. 2011 Nov. 2011 Jul. 2012 Jul. 2013 HMT451U6MFR8C Remark
Rev. 1.1 / Jul. 2013
2
Free Datasheet http://www.datasheet4u.com/
Description
SK hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR3 SDRAM devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations.
Feature
• VDD=1.5V +/- 0.075V • VDDQ=1.5V +/- 0.075V • VDDSPD=3.0V to 3.6V • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600,PC3-8600 • Bi-directional Differential Data Strobe • 8 bit pre-fetch • Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4 • Supports ECC error correction and detection • On Die Termination (ODT) supported • Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM • This product is in Compliance with the RoHS directive
Ordering Information
Part Number HMT451U6MFR8C-G7/H9/PB HMT41GU6MFR8C-G7/H9/PB/RD HMT41GU7MFR8C-G7/H9/PB Density 4GB 8GB 8GB Organization 512Mx64 1Gx64 1Gx72 Component Composition 512Mx8(H5TQ4G83MFR)*8 512Mx8(H5TQ4G83MFR)*16 512Mx8(H5TQ4G83MFR)*18 # of ranks 1 2 2 FDHS X X X
Rev. 1.1 / Jul. 2013
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Free Datasheet http://www.datasheet4u.com/
Key Parameters
MT/s DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Grade -G7 -H9 -PB -RD tCK (ns) 1.875 1.5 1.25 1.07 CAS Latency (tCK) 7 9 11 13 tRCD (ns) 13.125 tRP (ns) 13.125 tRAS (ns) 37.5 36 35 34 tRC (ns) 50.625 49.5 (49.125)* 48.75 (48.125)* 47.91 (47.125)* CL-tRCD-tRP 7-7-7 9-9-9 11-11-11 13-13-13
13.5 13.5 (13.125)* (13.125)* 13.75 13.75 (13.125)* (13.125)* 13.91 13.91 (13.125)* (13.125)*
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz] Grade CL6 -G7 -H9 -PB -RD 800 800 800 800 CL7 1066 1066 1066 1066 CL8 1066 1066 1066 1066 1333 1333 1333 1333 1333 1333 1600 1600 1866 CL9 CL10 CL11 CL12 CL13 Remark
Address Table
4GB(1Rx8) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB 8GB(2Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB 8GB(2Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB
Rev. 1.1 / Jul. 2013
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Free Datasheet http://www.datasheet4u.com/
Pin Descriptions
Pin Name A0–A15 BA0–BA2 RAS CAS WE S0–S1 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 DM0–DM8 CK0–CK1 CK0–CK1 Description SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) Pin Name SCL SDA SA0–SA2 VDD* VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RSVD Description I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use -
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
Rev. 1.1 / Jul. 2013
5
Free Datasheet http://www.datasheet4u.com/
Input/Output Functional Descriptions
Symbol CK0–CK1 CK0–CK1 Type Polarity Differential crossing Function CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This signal provides for external rank selection on systems with multiple ranks. RAS, CAS, and WE (ALONG WITH S) define the command being entered. When high, term.