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HMT451S6MFR8A Dataheets PDF



Part Number HMT451S6MFR8A
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description DDR3L SDRAM
Datasheet HMT451S6MFR8A DatasheetHMT451S6MFR8A Datasheet (PDF)

204pin DDR3L SDRAM SODIMM DDR3L SDRAM Unbuffered SODIMMs Based on 4Gb M-die HMT425S6MFR6A HMT451S6MFR8A HMT41GS6MFR8A * SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Jul. 2012 1 Free Datasheet http://www.datasheet4u.com/ Revision History Revision No. 0.1 0.2 1.0 History Initial Release JEDEC Spec, IDD(x16) Updated JEDEC Spec Updated Draft Date Sep. 2011 Nov. 2011 Jul. 2012 Remark Preliminary Rev. 1.0 / Jul. 2012 2 Free Datasheet http://www.d.

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204pin DDR3L SDRAM SODIMM DDR3L SDRAM Unbuffered SODIMMs Based on 4Gb M-die HMT425S6MFR6A HMT451S6MFR8A HMT41GS6MFR8A * SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Jul. 2012 1 Free Datasheet http://www.datasheet4u.com/ Revision History Revision No. 0.1 0.2 1.0 History Initial Release JEDEC Spec, IDD(x16) Updated JEDEC Spec Updated Draft Date Sep. 2011 Nov. 2011 Jul. 2012 Remark Preliminary Rev. 1.0 / Jul. 2012 2 Free Datasheet http://www.datasheet4u.com/ Description SK hynix Unbuffered Small Outline DDR3L SDRAM DIMMs (Unbuffered Small Outline Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices. These Unbuffered DDR3L SDRAM SODIMMs are intended for use as main memory when installed in systems such as mobile personal computers. Features • • • • • • • • • • • Power Supply: VDD=1.35V (1.283V to 1.45V) VDDQ = 1.35V (1.283V to 1.45V) VDDSPD=3.0V to 3.6V Backward Compatible with 1.5V DDR3 Memory module 8 internal banks Data transfer rates: PC3-12800, PC3-10600 Bi-directional Differential Data Strobe 8 bit pre-fetch Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4 On Die Termination (ODT) supported This product is in Compliance with the RoHS directive Ordering Information Part Number HMT425S6MFR6A-G7/H9/PB HMT451S6MFR8A-G7/H9/PB HMT41GS6MFR8A-G7/H9/PB Density 2GB 4GB 8GB Organization 256Mx64 512Mx64 1Gx64 Component Composition 256Mx16(H5TC4G63MFR)*4 512Mx8(H5TC4G83MFR)*8 512Mx8(H5TC4G83MFR)*16 # of ranks 1 1 2 Rev. 1.0 / Jul. 2012 3 Free Datasheet http://www.datasheet4u.com/ Key Parameters MT/s DDR3L-1066 DDR3L-1333 DDR3L-1600 Grade -G7 -H9 -PB tCK (ns) 1.875 1.5 1.25 CAS Latency (tCK) 7 9 11 tRCD (ns) 13.125 tRP (ns) 13.125 tRAS (ns) 37.5 36 35 tRC (ns) 50.625 49.5 (49.125)* 48.75 (48.125)* CL-tRCD-tRP 7-7-7 9-9-9 11-11-11 13.5 13.5 (13.125)* (13.125)* 13.75 13.75 (13.125)* (13.125)* *SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match. Speed Grade Frequency [MHz] Grade CL5 -G7 -H9 -PB 667 667 667 CL6 800 800 800 CL7 1066 1066 1066 CL8 1066 1066 1066 1333 1333 1333 1333 1600 CL9 CL10 CL11 CL12 Remark Address Table 2GB(1Rx16) Refresh Method Row Address Column Address Bank Address Page Size 8K/64ms A0-A14 A0-A9 BA0-BA2 2KB 4GB(1Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB 8GB(2Rx8) 8K/64ms A0-A15 A0-A9 BA0-BA2 1KB Rev. 1.0 / Jul. 2012 4 Free Datasheet http://www.datasheet4u.com/ Pin Descriptions Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS WE S[1:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Description Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses On Die Termination Inputs Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs Num ber 2 2 2 1 1 1 2 14 1 1 3 2 1 1 2 VREFDQ VREFCA VTT VDDSPD NC Input/Output Reference Termination Voltage SPD Power Reserved for future use 1 1 2 1 2 Total: 204 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] EVENT TEST RESET VDD VSS Description Data Input/Output Data Masks Data strobes Data strobes, negative line Temperature event pin Logic Analyzer specific test pin (No connect on SODIMM) Reset Pin Core and I/O Power Ground Num ber 64 8 8 8 1 1 1 18 52 Rev. 1.0 / Jul. 2012 5 Free Datasheet http://www.datasheet4u.com/ Input/Output Functional Descriptions Symbol CK0/CK0 CK1/CK1 Type Polarity Function IN The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is Cross Point driven from the clock inputs and output timing for read operations is synchronized to the input clock. Active High Activates the DDR3L SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. Enables the associated DDR3L SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3L SDRAM mode register. When sampled at the cross point of the rising edge of CK, signals CAS, RAS, and WE define the operation to be executed by the SDRAM. Reference voltage for SSTL15 inputs. — Selects which SDRAM internal bank of eight is activated. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read of Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addit.


HMT425S6MFR6A HMT451S6MFR8A HMT41GS6MFR8A


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