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IS42VM32100C Dataheets PDF



Part Number IS42VM32100C
Manufacturers ISSI
Logo ISSI
Description 512K x 32Bits x 2Banks Low Power Synchronous DRAM
Datasheet IS42VM32100C DatasheetIS42VM32100C Datasheet (PDF)

IS42SM32100C IS42RM32100C IS42VM32100C 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These IS42SM/RM/VM32100C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and ou.

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IS42SM32100C IS42RM32100C IS42VM32100C 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These IS42SM/RM/VM32100C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features  JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle / 64ms. • Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. • Programmable CAS Latency : 2,3 clocks. • Programmable Driver Strength Control - Full Strength or 1/2, 1/4, 1/8 of Full Strength • Deep Power Down Mode. • All inputs and outputs referenced to the positive edge of the system clock. • Data mask function by DQM. • Internal dual banks operation. • Burst Read Single Write operation. • Special Function Support. - PASR(Partial Array Self Refresh) - Auto TCSR(Temperature Compensated Self Refresh) • Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge. Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Rev. A | Mar. 2011 www.issi.com - [email protected] 1 Free Datasheet http://www.datasheet4u.com/ IS42SM/RM/VM32100C Figure1: 90Ball FBGA Ball Assignment 1 A DQ26 B DQ28 C VSSQ D VSSQ E VDDQ F G H J VSS A4 A7 CLK 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 4 5 6 7 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA /CAS VDD DQ6 DQ1 VDDQ VDD 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 NC /CS /WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 NC /RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 K DQM1 L VDDQ M VSSQ N VSSQ P DQ11 R DQ13 [Top View] Rev. A | Mar. 2011 www.issi.com - [email protected] 2 Free Datasheet http://www.datasheet4u.com/ IS42SM/RM/VM32100C Table2: Pin Descriptions Pin CLK Pin Name System Clock Descriptions The system clock input. All other inputs are registered to the SDRAM on the rising edge CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Enable or disable all inputs except CLK, CKE and DQM. Selects bank to be activated during RAS activity. Selects bank to be read/written during CAS activity. Row Address Column Address Auto Precharge : RA0~RA10 : CA0~CA7 : A10 CKE /CS BA Clock Enable Chip Select Bank Address A0~A10 Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection /RAS, /CAS, /WE RAS, CAS and WE define the operation. Refer function truth table for details. Controls output buffers in read mode and masks input data in write mode. Data input/output pin. Power supply for internal circuits and input buffers. Power supply for output buffers. No connection. DQM0~DQM3 DQ0~DQ31 VDD/VSS VDDQ/VSSQ NC Rev. A | Mar. 2011 www.issi.com - [email protected] 3 Free Datasheet http://www.datasheet4u.com/ IS42SM/RM/VM32100C Figure2: Functional Block Diagram CLK CKE EXTENDED MODE REGISTER CLOCK GENERATOR TCSR PASR ADDRESS ROW ADDRESS BUFFER & REFRESH COUNTER BANK B BANK A ROW DECODER ROW DECODER MODE REGISTER SENSE AMPLIFIER /CS /RAS /CAS /WE COLUMN ADDRESS BUFFER & BURST COUNTER COLUMN DECODER & LATCH CIRCUIT Rev. A | Mar. 2011 COMMAND DECODER CONTROL LOGIC DATA CONTROL CIRCUIT DQM LATCH CIRCUIT INPUT & OUTPUT BUFFER DQ www.issi.com - [email protected] 4 Free Datasheet http://www.datasheet4u.com/ IS42SM/RM/VM32100C Figure3: Simplified State Diagram EXTENDED MODE REGISTER SET SELF REFRESH .


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