Document
MGA-43828 925–960 MHz Linear Power Amplifier Module
Data Sheet
Description
The Avago MGA-43828 is a fully matched, highly linear power amplifier (PA) designed for use in the 925-960 MHz band. Based on Avago’s proprietary 0.25 µm GaAs E-pHEMT technology, the device features high linearity, gain and power-added efficiency (PAE) with integrated power detector and shutdown functions. The MGA-43828 is ideal for use as a final stage PA for Small Cell base transceiver station (BTS) applications.
Component Image
(5.0 × 5.0 × 0.9) mm Package Outline
AVAGO 43828 YYWW XXXX
TOP VIEW
Pin Configuration
Notes: Package marking provides orientation and identification ”43828” = Device part number ”YYWW” = Year and work week ”XXXX” = Assembly lot number
28 NC 27 Gnd 26 Vdd2 25 Gnd 24 Vdd3 23 Vdd3 22 Vdd3
Gnd 1 Gnd 2 NC 3 RFin 4 NC 5 Gnd 6 NC 7
(5.0 x 5.0 x 0.9) mm
21 Gnd 20 Gnd 19 RFout 18 RFout 17 RFout 16 Gnd 15 Gnd
Features
• High linearity performance : Max -50 dBc ACLR1[1] at 27 dBm linear output power (biased with 5.0 V supply)
• High gain: 33 dB • Good efficiency • Fully matched • Built-in detector • GaAs E-pHEMT Technology[2] • Low cost small package size: (5.0 × 5.0 × 0.9) mm • MSL3 • Lead free/Halogen free/RoHS compliance
Specifications
940 MHz; 5.0 V, Idqtotal =316 mA (typ), W-CDMA Test model #1, 64DPCH downlink signal
• PAE: 14.7% • 27 dBm linear Pout @ ACLR1 = -50 dBc[1] • 33 dB Gain • Detector range: 20 dB
Applications
• Final stage high linearity amplifier for Picocell and Enterprise Femtocell PA targeted for small cell BTS downlink applications.
Notes: 1. W-CDMA Test model #1, 64DPCH downlink signal 2. Enhancement mode technology employs positive VGS, thereby
eliminating the need of negative gate voltage associated with conventional depletion mode devices.
Functional Block Diagram
Vdd2 Vdd3
NC 8 Vc2 9 Vc3 10 Gnd 11 VddBias 12 Gnd 13 Vdet 14
Attention: Observe Precautions for handling electrostatic sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 400 V Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control.
RFin
2nd Stage 3rd Stage
RFout
Biasing Circuit Vc2 Vc3 VddBias Vdet
Absolute Maximum Rating [1] TA=25 °C
Symbol
Parameter
Vdd, VddBias Vc Pin,max Pdiss Tj
Supply voltages, bias supply voltage Control Voltage CW RF Input Power Total Power Dissipation [3] Junction Temperature
TSTG Storage Temperature
Units V V dBm W °C °C
Absolute Max. 6.0 (Vdd) 20 4.9 150 -65 to 150
Thermal Resistance [2,3]
qjc = 12 °C/W Notes: 1. Operation of this device in excess of any of
these limits may cause permanent damage. 2. Thermal resistance measured using Infra-
Red Measurement Technique. 3. Board temperature (TB) is 25 °C , for TB >91
°C derate the device power at 83 mW per °C rise in Board (package belly) temperature.
Electrical Specifications TA = 25 °C, Vdd = VddBias = 5.0 V, Vc2=3.5 V, Vc3=2.8 V, Idqtotal = 316 mA, RF performance at 940 MHz, W-CDMA Test model #1, 64DPCH downlink signal operation, unless otherwise stated.
Symbol Vdd Idqtotal Gain OP1dB ACLR1 @ Pout=27.0 dBm PAE |S11| DetR 2fo
Parameter and Test Condition Supply Voltage Quiescent Supply Current Gain Output Power at 1dB Gain Compression W-CDMA Test model #1, 64DPCH downlink signal Power Added Efficiency Input Return Loss, 50 Ω source Detector RF dynamic range 2fo Harmonics (W-CDMA Test model #1, 64DPCH downlink signal)
Units Min. Typ. Max.
V-
5.0 -
mA -
316 560
dB 31 33 -
dBm -
36 -
dBc -
-50 -
% 13 14.7 -
dB -
13.9 -
dB -
20 -
dBc -35
2
Product Consistency Distribution Charts [1]
LSL
LSL
31 32
33 34
35 36
Figure 1. Gain at Pout=27 dBm, LSL= 31 dB, nominal = 33 dB
USL
13 14 15 16 17 Figure 2. PAE at Pout=27 dBm, LSL=13%, nominal = 14.7%
200 250 300 350 400 450 500 550 600 Figure 3. Idqtotal, Nominal = 316 mA, USL=560 mA
600 650 700 750 800 850 Figure 4. Idd_Total at Pout=27 dBm, nominal = 687 mA
900
-60 -58 -56 -54 -52 -50 -48 -46 -44 -42 Figure 5. ACLR1 at Pout=27 dBm, nominal = -50.3 dBc Note: 1. Distribution data sample size is 1500 samples taken from three wafer lots. TA = 25 °C, Vdd=VddBias = 5.0 V, Vc2 = 3.5 V, Vc3 = 2.8 V, RF performance
at 940 MHz, unless otherwise stated. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits.
3
MGA-43828 typical over-temperature performance at Vc2=3.5 V, Vc3=2.8 V (Vdd=VddBias=5 V) as shown in Figure 27 and Vc2= 3.6 V, Vc3=2.5 V (Vdd=VddBias=5.5 V), unless otherwise stated.
S21,S11,S22/dB
40
35 30 25
S21
85°C 25°C
-40°C
20
15
10
5 0
S22
-5
-10 -15
S11
-20
-25
-30
-35
-400.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2
Frequency/GHz
S21,S11,S22/dB
40
35 30 25 20
S21 85°C 25°C -40°C
15
10
5 0
S22
-5
-10 -15
S11
-20
-25
-30
-35
-400.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1.