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GHz SoC. AR9331 Datasheet

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GHz SoC. AR9331 Datasheet






AR9331 SoC. Datasheet pdf. Equivalent




AR9331 SoC. Datasheet pdf. Equivalent





Part

AR9331

Description

Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC



Feature


Data Sheet PRELIMINARY December 2010 AR9 331 Highly-Integrated and Cost Effectiv e IEEE 802.11n 1x1 2.4 GHz SoC for AP a nd Router Platforms General Descriptio n The Atheros AR9331 is a highly integr ated and cost effective IEEE 802.11n 1x 1 2.4 GHz Systemon-a-Chip (SoC) for wir eless local area network (WLAN) AP and router platforms. In a single chip, the AR9331 includes a.
Manufacture

Atheros

Datasheet
Download AR9331 Datasheet


Atheros AR9331

AR9331; MIPS 24K processor, five-port IEEE 802. 3 Fast Ethernet Switch with MAC/PHY, on e USB 2.0 MAC/PHY, and external memory interface for serial Flash, SDRAM, DDR1 or DDR2, I2S/SPDIF-Out audio interface , SLIC VOIP/PCM interface, UART, and GP IOs that can be used for LED controls o r other general purpose interface confi gurations. The AR9331 integrates two Gb it MACs plus a fiv.


Atheros AR9331

e-port Fast Ethernet switch with a four- traffic class Quality of Service (QoS) engine. The AR9331 integrates an 802.11 n 1x1 MAC/BB/ radio with internal PA an d LNA. It supports 802.11n operations u p to 72 Mbps for 20 MHz and 150 Mbps fo r 40 MHz channel respecti .


Atheros AR9331

.

Part

AR9331

Description

Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC



Feature


Data Sheet PRELIMINARY December 2010 AR9 331 Highly-Integrated and Cost Effectiv e IEEE 802.11n 1x1 2.4 GHz SoC for AP a nd Router Platforms General Descriptio n The Atheros AR9331 is a highly integr ated and cost effective IEEE 802.11n 1x 1 2.4 GHz Systemon-a-Chip (SoC) for wir eless local area network (WLAN) AP and router platforms. In a single chip, the AR9331 includes a.
Manufacture

Atheros

Datasheet
Download AR9331 Datasheet




 AR9331
Data Sheet
PRELIMINARY
December 2010
AR9331 Highly-Integrated and Cost Effective IEEE 802.11n
1x1 2.4 GHz SoC for AP and Router Platforms
General Description
The Atheros AR9331 is a highly integrated and
cost effective IEEE 802.11n 1x1 2.4 GHz System-
on-a-Chip (SoC) for wireless local area network
(WLAN) AP and router platforms.
In a single chip, the AR9331 includes a MIPS 24K
processor, five-port IEEE 802.3 Fast Ethernet
Switch with MAC/PHY, one USB 2.0 MAC/PHY,
and external memory interface for serial Flash,
SDRAM, DDR1 or DDR2, I2S/SPDIF-Out audio
interface, SLIC VOIP/PCM interface, UART, and
GPIOs that can be used for LED controls or other
general purpose interface configurations.
The AR9331 integrates two Gbit MACs plus a
five-port Fast Ethernet switch with a four-traffic
class Quality of Service (QoS) engine.
The AR9331 integrates an 802.11n 1x1 MAC/BB/
radio with internal PA and LNA. It supports
802.11n operations up to 72 Mbps for 20 MHz
and 150 Mbps for 40 MHz channel respectively,
and IEEE 802.11b/g data rates. Additional
features include on-chip one-time programmable
(OTP) memory.
System Block Diagram
Features
Complete IEEE 802.11n 1x1 AP or router in a
single chip
MIPS 24K processor operating at up to
400 MHz
External 16-bit DDR1, DDR2, or SDRAM
memory interface
SPI NOR Flash memory support
No external EEPROM needed
4 LAN ports and 1 WAN port IEEE 802.3 Fast
Ethernet switch with auto-crossover, auto
polarity, and auto-negotiation in PHYs
Four classes of QoS per port
Fully integrated RF front-end including PA
and LNA
Optional external LNA/PA
Switched antenna diversity
High-speed UART for console support
I2S/SPDIF-out audio interface
SLIC for VOIP/PCM
USB 2.0 host/device mode support
GPIO/LED support
JTAG-based processor debugging supported
25 MHz or 40 MHz reference clock input
Advanced power management with dynamic
clock switching for ultra-low power modes
148-pin, 12 mm x 12 mm dual-row LPCC
package
2.4 GHz
RF
Front
End
802.11n
1x1 WLAN
MAC/BB/
Radio
Internal
SRAM
I-Cache
D-Cache
AR9331
SDRAM/
DDR1/DDR2
Controller and
NOR Flash
Memory
Interface
MIPS 24K
Processor
5x Fast Ethernet
LAN/WAN Ports
UART
USB MAC/PHY
External Interface
I2S/SPDIF
SLIC
Serial Flash and SDRAM/DDR Interface
5x Fast Ethernet Ports
UART Interface
USB 2.0 Interface
GPIOs/LEDs
Audio Interface
VOIP/PCM
25 or 40 MHz Crystal
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™,
Ethos™, Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The
Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1
Free Datasheet http://www.datasheet4u.com/




 AR9331
PRELIMINARY
2 • AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms
2 December 2010
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
Free Datasheet http://www.datasheet4u.com/




 AR9331
PRELIMINARY
Table of Contents
1 Pin Descriptions .......................... 13
2 Functional Description ............... 21
2.1 MIPS Processor ....................................... 22
2.2 Configuration ......................................... 22
2.3 AR9331 Address MAP .......................... 23
2.4 AHB Master Bus ..................................... 23
2.5 APB Bridge .............................................. 23
2.6 DDR Memory Controller ...................... 23
2.7 Serial Flash (SPI) .................................... 24
2.8 UART ....................................................... 24
2.9 GE0 and GE1 ........................................... 25
2.10 MDC/MDIO Interface ......................... 25
2.11 Ethernet Switch Controller .................. 26
2.11.1 VLANs For LAN Ports ............... 28
2.11.2 Quality of Service (QoS) for LAN
Ports .............................................. 29
2.12 Rate Limiting ......................................... 29
2.13 Broadcast Storm Control ...................... 30
2.14 Switch Operation .................................. 30
2.15 Port Mirroring ....................................... 30
2.16 Port States ............................................... 30
3 Medium Access Control (MAC) 31
3.1 Overview ................................................. 31
3.2 Descriptor ................................................ 31
3.3 Descriptor Format .................................. 32
3.4 Queue Control Unit (QCU) .................. 47
3.5 DCF Control Unit (DCU) ...................... 47
3.5.1 DCU State Information .............. 48
3.6 Protocol Control Unit (PCU) ................ 48
4 Digital PHY Block ....................... 49
4.1 Overview ................................................. 49
4.2 802.11n Mode .......................................... 49
4.2.1 Transmitter (Tx) .......................... 49
4.2.2 Receiver (Rx) ............................... 49
4.3 802.11b/g Legacy Mode ........................ 50
4.3.1 Transmitter .................................. 50
4.3.2 Receiver ........................................ 50
5 Radio Block ...................................51
5.1 Receiver (Rx) Block ................................ 51
5.2 Transmitter (Tx) Block .......................... 51
5.3 Synthesizer (SYNTH) Block ................. 52
5.4 Bias/Control (BIAS) Block ................... 52
6 Register Descriptions ..................53
6.1 DDR Registers ........................................ 54
6.1.1 DRR DRAM Configuration
(DDR_CONFIG) ......................... 54
6.1.2 DDR DRAM Configuration 2
(DDR_CONFIG2) ....................... 55
6.1.3 DDR Mode Value
(DDR_MODE_REGISTER) ........ 55
6.1.4 DDR Extended Mode
(DDR_EXTENDED_MODE_REGIS
TER) .............................................. 55
6.1.5 DDR Control (DDR_CONTROL) 56
6.1.6 DDR Refresh Control and
Configuration (DDR_REFRESH) 56
6.1.7 DDR Read Data Capture Bit Mask
(DDR_RD_DATA_THIS_CYCLE)
56
6.1.8 DQS Delay Tap Control for Byte 0
(TAP_CONTROL_0) .................. 56
6.1.9 DQS Delay Tap Control for Byte 1
(TAP_CONTROL_1) .................. 57
6.1.10 GE0 Interface Write Buffer Flush
(DDR_WB_FLUSH_GE0) .......... 57
6.1.11 GE1 Interface Write Buffer Flush
(DDR_WB_FLUSH_GE1) .......... 57
6.1.12 USB Interface Write Buffer Flush
(DDR_WB_FLUSH_USB) .......... 57
6.1.13 AMBA Interface Write Buffer Flush
(DDR_WB_FLUSH_AMBA) ..... 58
6.1.14 DDR2 Configuration
(DDR_DDR2_CONFIG) ............. 58
6.1.15 DDR EMR2 (DDR_EMR2) ......... 58
6.1.16 DDR EMR3 (DDR_EMR3) ......... 58
6.1.17 DDR Burst Control (DDR_BURST)
59
6.1.18 AHB Master Timeout Control
(AHB_MASTER_TIMEOUT_MAX)
....................................................... 59
6.1.19 AHB Timeout Current Count
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms • 1
December 2010 1
Free Datasheet http://www.datasheet4u.com/



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